Automated Synthesis of High Performance Clock Distribution Networks

本研究是关于高速、高可靠性时钟分配网络的自动化综合。 为了控制同步操作，需要全局时钟信号，并且必须在精确的时间将其分配给每个寄存器。 本文研究了一个用于综合缓冲时钟分配网络的四阶段自顶向下设计系统。 正在开发包括工艺参数变化对时间的影响的操作模型。 在系统的行为级完成调度时钟偏移。 时钟分配算法被包括在一个集成的综合系统中。

This research is on automated synthesis of high speed, highly reliable clock distribution networks. A global clock signal is required in order to control synchronous operations, and it must be distributed to every register at a precise time. A four phase top-down design system for synthesizing buffered clock distribution networks is being investigated. Models of operation which include the effects of process parameter variations on timing are being developed. Scheduling clock skew is done at the behavioral level of the system. The clock distribution algorithms are being included in an integrated synthesis system.