CPA-DA: Integrated Methodology for Managing Noise in Next Generation Multi-Core SoCs

CPA-DA：在下一代多核SoC中管理噪声的集成方法提案编号0811317PI：Eby G.Friedman of Rochester摘要本项目的重点是开发一种集成的噪声管理方法，解决不同噪声源之间的多重相互作用，以支持下一代多核混合信号系统芯片(SoCs)的设计。将开发精确的、但计算高效的噪声模型，并将其与降噪技术相结合，以有效控制系统内的信号特征。利用通信中的经典噪声传播模型，将应用一种新的统一方法来模拟不同系统组件之间的噪声产生、传播和接收，以支持聚合噪声消除技术的开发。将研究缓解多个噪声源的影响的设计权衡，并制定设计指南。将研究器件、电路和多核级别的不同噪声影响之间的相互依赖关系，并将开发出将混合信号组件中的噪声降至最低的设计策略。重点将放在负责在不同系统部件之间产生和传播噪声的全局特征上，例如配电网络、全球互连线路、核心间同步方案和硅衬底。还将研究噪声模型和降噪技术对工艺和环境变化的敏感度。最终目标是，在这个项目完成后，将更好地理解模拟电路中的信号不确定性和由于多核SoC中的多重噪声效应而导致的数字电路中的延迟不确定性，并以计算高效的方式对其进行准确建模，同时将开发集成的降噪方法来设计下一代高复杂性、高性能的集成电路。这些研究成果将为更广泛的学术界针对大学教学和研究活动的教育倡议提供新的方向。将与研究生合作设计展示研究成果的实用方面的本科生项目。将开发一门与这项研究相关的课程，并为背景不同的研究生和大四本科生提供课程。将准备一份教程，供在主要会议上介绍。PI还将参加一个旨在提高少数族裔在工程和科学研究生项目中招生人数的大学项目。该项目的智力和社会目标旨在大大超越芯片上系统设计过程中的现有限制，使未来几代多核、混合信号SoC的开发成为可能，同时促进科学和工程劳动力的进步和多样性。

CPA-DA: Integrated Methodology for Managing Noise in Next Generation Multi-Core SoCsProposal No. 0811317PI: Eby G. FriedmanUniversity of RochesterAbstractThe focus of this project is the development of an integrated methodology for managing noise that addresses the multiple interactions among different noise sources to support the design of next generation multi-core mixed-signal systems-on-chips (SoCs). Accurate, yet computationally efficient noise models will be developed and combined with noise reduction techniques to effectively control the signal characteristics within a system. Leveraging the classical noise propagation model from communications, a novel unified approach will be applied to model noise generation, propagation, and reception among diverse system components, supporting the development of aggregate noise cancellation techniques. Design tradeoffs to alleviate the effects of multiple noise sources will be investigated and design guidelines will be developed. The interdependence among diverse noise effects at the device, circuit, and multi-core levels will be investigated and design strategies that minimize noise across mixed-signal components will be developed. Emphasis will be placed on the global features responsible for generating and propagating noise among different system components, such as the power distribution networks, the global interconnect lines, the inter-core synchronization schemes, and the silicon substrate. The sensitivity of the noise models and reduction techniques to process and environmental variations will also be investigated. The ultimate objective is that upon completion of this project, signal uncertainty in analog circuits and delay uncertainty in digital circuits due to multiple noise effects in multi-core SoCs will be better understood and accurately modeled in a computationally efficient manner, while integrated noise reduction methodologies will be developed to design the next generation of high complexity, high performance integrated circuits. These research results will provide new directions for educational initiatives targeting both university teaching and research activities in the broader academic community. Undergraduate projects demonstrating the practical aspects of the research results will be devised in collaboration with graduate students. A course related to the research will be developed and offered to graduate and senior undergraduate students with disparate backgrounds. A tutorial will be prepared for presentation at major conferences. The PI will also participate in a University program intended to enhance minority enrollment in graduate engineering and science programs. The intellectual and social objectives of this project are intended to greatly surpass existing limitations in the system-on-chip design process, enabling the development of future generations of multi-core, mixed-signal SoCs, while contributing towards the advancement and diversity of the science and engineering workforce.