CPA-DA: Integrated Methodology for Managing Noise in Next Generation Multi-Core SoCs

CPA-DA：下一代多核系统芯片噪声管理的集成方法。该项目的重点是开发一种集成的噪声管理方法，解决不同噪声源之间的多种相互作用，以支持下一代多核混合信号片上系统（SoC）的设计。将开发精确但计算效率高的噪声模型，并将其与降噪技术相结合，以有效地控制系统内的信号特性。利用通信中的经典噪声传播模型，将采用一种新的统一方法来模拟不同系统组件之间的噪声生成、传播和接收，支持聚合噪声消除技术的发展。将研究减轻多个噪声源影响的设计权衡，并制定设计指南。将研究器件、电路和多核级别的各种噪声效应之间的相互依赖关系，并制定最大限度地降低混合信号组件噪声的设计策略。重点将放在全球功能负责产生和传播不同的系统组件之间的噪声，如配电网络，全球互连线，内核间的同步计划，和硅基板。还将研究噪声模型和降噪技术对工艺和环境变化的敏感性。最终目标是，在完成该项目后，由于多核SoC中的多种噪声效应，模拟电路中的信号不确定性和数字电路中的延迟不确定性将得到更好的理解，并以计算高效的方式准确建模，同时将开发集成降噪方法来设计下一代高复杂度，高性能集成电路。这些研究成果将为针对大学教学和更广泛学术界的研究活动的教育举措提供新的方向。展示研究成果的实践方面的本科项目将与研究生合作设计。与研究相关的课程将开发和提供给研究生和高年级本科生与不同的背景。将编写一份教程，在主要会议上介绍。PI还将参加一个旨在提高研究生工程和科学课程少数民族入学率的大学项目。该项目的智力和社会目标旨在大大超越片上系统设计过程中的现有限制，实现未来几代多核混合信号SoC的开发，同时为科学和工程人员的进步和多样性做出贡献。

CPA-DA: Integrated Methodology for Managing Noise in Next Generation Multi-Core SoCsProposal No. 0811317PI: Eby G. FriedmanUniversity of RochesterAbstractThe focus of this project is the development of an integrated methodology for managing noise that addresses the multiple interactions among different noise sources to support the design of next generation multi-core mixed-signal systems-on-chips (SoCs). Accurate, yet computationally efficient noise models will be developed and combined with noise reduction techniques to effectively control the signal characteristics within a system. Leveraging the classical noise propagation model from communications, a novel unified approach will be applied to model noise generation, propagation, and reception among diverse system components, supporting the development of aggregate noise cancellation techniques. Design tradeoffs to alleviate the effects of multiple noise sources will be investigated and design guidelines will be developed. The interdependence among diverse noise effects at the device, circuit, and multi-core levels will be investigated and design strategies that minimize noise across mixed-signal components will be developed. Emphasis will be placed on the global features responsible for generating and propagating noise among different system components, such as the power distribution networks, the global interconnect lines, the inter-core synchronization schemes, and the silicon substrate. The sensitivity of the noise models and reduction techniques to process and environmental variations will also be investigated. The ultimate objective is that upon completion of this project, signal uncertainty in analog circuits and delay uncertainty in digital circuits due to multiple noise effects in multi-core SoCs will be better understood and accurately modeled in a computationally efficient manner, while integrated noise reduction methodologies will be developed to design the next generation of high complexity, high performance integrated circuits. These research results will provide new directions for educational initiatives targeting both university teaching and research activities in the broader academic community. Undergraduate projects demonstrating the practical aspects of the research results will be devised in collaboration with graduate students. A course related to the research will be developed and offered to graduate and senior undergraduate students with disparate backgrounds. A tutorial will be prepared for presentation at major conferences. The PI will also participate in a University program intended to enhance minority enrollment in graduate engineering and science programs. The intellectual and social objectives of this project are intended to greatly surpass existing limitations in the system-on-chip design process, enabling the development of future generations of multi-core, mixed-signal SoCs, while contributing towards the advancement and diversity of the science and engineering workforce.