CPA-DA: Integrated Methodology for Managing Noise in Next Generation Multi-Core SoCs

CPA-DA：下一代多核soc中噪声管理的集成方法提案号0811317PI: Eby G. FriedmanUniversity of rochester摘要本项目的重点是开发一种集成的噪声管理方法，该方法解决了不同噪声源之间的多重相互作用，以支持下一代多核混合信号片上系统（soc）的设计。将开发精确的、计算效率高的噪声模型，并将其与降噪技术相结合，以有效地控制系统内的信号特性。利用通信中的经典噪声传播模型，将采用一种新的统一方法来模拟不同系统组件之间的噪声产生、传播和接收，从而支持聚合噪声消除技术的发展。我们会研究如何权衡设计，以减轻多个噪声源的影响，并制订设计指引。将研究器件、电路和多核级不同噪声效应之间的相互依存关系，并开发将混合信号组件噪声降至最低的设计策略。重点将放在负责在不同系统组件之间产生和传播噪声的全局特征上，例如配电网络、全局互连线、核间同步方案和硅衬底。噪音模型和减少技术对过程和环境变化的敏感性也将被调查。最终目标是在该项目完成后，模拟电路中的信号不确定性和数字电路中由于多核soc中多重噪声影响而导致的延迟不确定性将以计算高效的方式得到更好的理解和准确的建模，同时将开发集成降噪方法来设计下一代高复杂性，高性能集成电路。这些研究成果将为更广泛的学术界针对大学教学和研究活动的教育活动提供新的方向。展示研究成果的实际方面的本科生项目将与研究生合作设计。与研究相关的课程将被开发并提供给具有不同背景的研究生和大四本科生。将编写一份指南，以便在主要会议上发表。PI还将参与一项旨在提高少数族裔在工程和科学研究生课程中的入学率的大学计划。该项目的智力和社会目标旨在大大超越片上系统设计过程中的现有限制，使未来几代多核混合信号soc的发展成为可能，同时为科学和工程劳动力的进步和多样性做出贡献。

CPA-DA: Integrated Methodology for Managing Noise in Next Generation Multi-Core SoCsProposal No. 0811317PI: Eby G. FriedmanUniversity of RochesterAbstractThe focus of this project is the development of an integrated methodology for managing noise that addresses the multiple interactions among different noise sources to support the design of next generation multi-core mixed-signal systems-on-chips (SoCs). Accurate, yet computationally efficient noise models will be developed and combined with noise reduction techniques to effectively control the signal characteristics within a system. Leveraging the classical noise propagation model from communications, a novel unified approach will be applied to model noise generation, propagation, and reception among diverse system components, supporting the development of aggregate noise cancellation techniques. Design tradeoffs to alleviate the effects of multiple noise sources will be investigated and design guidelines will be developed. The interdependence among diverse noise effects at the device, circuit, and multi-core levels will be investigated and design strategies that minimize noise across mixed-signal components will be developed. Emphasis will be placed on the global features responsible for generating and propagating noise among different system components, such as the power distribution networks, the global interconnect lines, the inter-core synchronization schemes, and the silicon substrate. The sensitivity of the noise models and reduction techniques to process and environmental variations will also be investigated. The ultimate objective is that upon completion of this project, signal uncertainty in analog circuits and delay uncertainty in digital circuits due to multiple noise effects in multi-core SoCs will be better understood and accurately modeled in a computationally efficient manner, while integrated noise reduction methodologies will be developed to design the next generation of high complexity, high performance integrated circuits. These research results will provide new directions for educational initiatives targeting both university teaching and research activities in the broader academic community. Undergraduate projects demonstrating the practical aspects of the research results will be devised in collaboration with graduate students. A course related to the research will be developed and offered to graduate and senior undergraduate students with disparate backgrounds. A tutorial will be prepared for presentation at major conferences. The PI will also participate in a University program intended to enhance minority enrollment in graduate engineering and science programs. The intellectual and social objectives of this project are intended to greatly surpass existing limitations in the system-on-chip design process, enabling the development of future generations of multi-core, mixed-signal SoCs, while contributing towards the advancement and diversity of the science and engineering workforce.