Architecture and Synthesis Techniques for Embedded Systems
Architecture and Synthesis Techniques for Embedded Systems
批准号:
9501615
负责人:
Rajesh Gupta
金额:
$11.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
1995
资助国家:
美国
项目状态:
已结题
起止时间:
1995-05-01 至 1998-04-30
中文摘要
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英文摘要
This research is on synthesis techniques for micro-electronics- based "embedded systems". An embedded system is one designed for a specific functionality under stringent constraints on its timing performance and cost. Design automation techniques are being developed for use in a framework where the designer can assess tradeoffs between various embedded system architectures and designs. The main capabilities of this framework are: (a) timing analysis for both execution delay and rate constraints; (b) embeddable software and runtime system generation under timing constrains; (c) software size-performance tradeoffs; (d) cost- performance analysis of architectural alternatives, such as pre- fetch and forward hardware. This work is exploreing system partitioning and transformation techniques to build system implementations that "guarantee" constraint satisfaction while optimizing system development cost.
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资助金额:$4.0万
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财政年份:1998
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