Modeling and Optimization of Thermal and Energy Efficient Processing in Multi-Core System-Chips

题目：多核系统芯片中热和节能处理的建模和优化名称：Rajesh GuptaPI所在机构：加州大学圣地亚哥分校多核系统芯片，或芯片多处理器（cmp），对新一代计算机系统架构师和实现者来说既是机遇也是挑战。然而，由于集成芯片的散热能力缺乏可扩展性，以节能的方式开发额外的处理资源是一项挑战。在各种电路、逻辑或架构设计层面使用最知名的低功耗设计方法不足以实现多核性能改进的潜力。相反，系统的架构必须推动热极限，以最大限度地利用可用的散热极限，无论是静态还是动态。本提案旨在为节能CMP系统构建一个框架，使系统架构师能够以系统的方式做出各种与电源相关的决策，从选择关机和减速状态到对速度扩展和负载平衡的架构支持。该方法依赖于将速度缩放问题及其在各种约束条件下的不同实例表述为优化问题。优化问题不仅要考虑封装效应，还要考虑整个CMP模具的散热空间分布。由于先进的工艺，低电压（例如，亚阈值）电路操作以及由于不受关闭或减速措施影响的块引起的“架构泄漏”，泄漏功率越来越重要，因此需要特别关注。PIs对泄漏的处理基于两个关键概念：有效地确定临界速度的运行时间，从而提供最佳的节能处理；调度方法从全局角度观察系统级的功耗，并利用电源状态变化的灵活性来实现有效的负载均衡和延迟隐藏效果。PI还试图通过使应用程序开发人员能够使用功率感知API（例如，可以根据当前能源可用性配置文件更改算法和精度）显式地编程重要的特定于应用程序的“元数据”来捕获应用程序意图。该项目的智力优势在于优化技术，寻求多种减速和关闭状态的明智平衡，以最有效地利用能源，同时突破物理放置和包装限制所支持的热极限。拟议研究的更广泛影响是它对与热感知节能嵌入式处理主题相关的各种课程和项目的基础设施的贡献。该项目旨在为学生提供学习和实验操作系统内部、内存接口和限时计算的机会。

Proposal ID: 0702792Title: Modeling and Optimization of Thermal and Energy Efficient Processing in Multi-Core System-ChipsPI name: Rajesh GuptaPI Inst: UC SanDiego Multi-Core System-Chips, or Chip Multi Processors (CMPs), represent both an opportunity as well as a challenge to the new generation of computer system architects and implementers. However, the exploitation of additional processing resources in an energy efficient manner is a challenge due to lack of scalability of the heat dissipation capabilities of the integrated chips. Use of best known methods for low power design at various circuit, logic or architectural design levels is not enough to realize the potential for multi-core performance improvement. Instead, systems must be architected to push the thermal limits to take the maximum advantage of the available heat dissipation limits, both statically as well as dynamically. This proposal seeks to build a framework for energy-efficient CMP systems that enables the system architect to make various power related decisions from the choice of shutdown and slowdown states to architectural support for speed scaling and load balancing -- in a systematic manner. The approach relies upon the formulation of the speed scaling problem and its different instances under various constraints as an optimization problem. The optimization problem takes into account not only package effects, but also spatial distribution of heat dissipation across the CMP die. Particular attention is paid to leakage power, given its growing importance due to the advancing processes, low voltage (e.g., sub-threshold) circuit operations and due to 'architectural leakage' caused by blocks that are not subject to shutdown or slowdown measures. The PIs treatment of leakage is based on two key concepts: efficient runtime determination of a critical speed that provides optimum energy efficient processing; and scheduling methods that takes a global view of the system level power consumption and exploit the flexibility to make power state changes to achieve effective load-balancing and latency hiding effects. The PI also seek to capture the application intent by enabling the application developer to explicitly program important application-specific 'metadata' using a power-aware API (that, for instance, may change algorithms, precision based on current energy availability profile). The intellectual merit of the project is in optimization techniques that seek a judicious balance of multiple slowdown and shutdown states for the most efficient utilization of energy while pushing the thermal limits supported by the physical placement and packaging constraints. The broader impact of the proposed research is its contribution to an infrastructure of various courses and projects related to the topic of thermally aware energy efficient embedded processing. The project seeks to provide students chance to learn and experiment with the OS internals, memory interfaces and time-bound computations.