Modeling and Optimization of Thermal and Energy Efficient Processing in Multi-Core System-Chips

多核系统芯片热能高效处理的建模和优化

• 批准号: 0702792
• 负责人: Rajesh Gupta
• 金额: --
• 依托单位: University of California-San Diego
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-08-01 至 2010-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0702792&HistoricalAwards=false
• 关键词: Modeling; Optimization; Thermal; Energy; Efficient

Proposal ID: 0702792Title: Modeling and Optimization of Thermal and Energy Efficient Processing in Multi-Core System-ChipsPI name: Rajesh GuptaPI Inst: UC SanDiego Multi-Core System-Chips, or Chip Multi Processors (CMPs), represent both an opportunity as well as a challenge to the new generation of computer system architects and implementers. However, the exploitation of additional processing resources in an energy efficient manner is a challenge due to lack of scalability of the heat dissipation capabilities of the integrated chips. Use of best known methods for low power design at various circuit, logic or architectural design levels is not enough to realize the potential for multi-core performance improvement. Instead, systems must be architected to push the thermal limits to take the maximum advantage of the available heat dissipation limits, both statically as well as dynamically. This proposal seeks to build a framework for energy-efficient CMP systems that enables the system architect to make various power related decisions from the choice of shutdown and slowdown states to architectural support for speed scaling and load balancing -- in a systematic manner. The approach relies upon the formulation of the speed scaling problem and its different instances under various constraints as an optimization problem. The optimization problem takes into account not only package effects, but also spatial distribution of heat dissipation across the CMP die. Particular attention is paid to leakage power, given its growing importance due to the advancing processes, low voltage (e.g., sub-threshold) circuit operations and due to 'architectural leakage' caused by blocks that are not subject to shutdown or slowdown measures. The PIs treatment of leakage is based on two key concepts: efficient runtime determination of a critical speed that provides optimum energy efficient processing; and scheduling methods that takes a global view of the system level power consumption and exploit the flexibility to make power state changes to achieve effective load-balancing and latency hiding effects. The PI also seek to capture the application intent by enabling the application developer to explicitly program important application-specific 'metadata' using a power-aware API (that, for instance, may change algorithms, precision based on current energy availability profile). The intellectual merit of the project is in optimization techniques that seek a judicious balance of multiple slowdown and shutdown states for the most efficient utilization of energy while pushing the thermal limits supported by the physical placement and packaging constraints. The broader impact of the proposed research is its contribution to an infrastructure of various courses and projects related to the topic of thermally aware energy efficient embedded processing. The project seeks to provide students chance to learn and experiment with the OS internals, memory interfaces and time-bound computations.

提案ID：0702792标题：多核系统芯片中的热量和能量有效处理的建模和优化PI姓名：Rajesh Gupta PI Inst：UC SanDiego多核系统芯片，或芯片多处理器（CMP），对新一代计算机系统架构师和实现者来说既是机遇也是挑战。然而，由于集成芯片的散热能力缺乏可扩展性，以节能方式利用额外的处理资源是一个挑战。在各种电路、逻辑或架构设计级别上使用用于低功率设计的最佳已知方法不足以实现多核性能改进的潜力。相反，系统的架构必须推动热限制，以最大限度地利用可用的散热限制，无论是静态还是动态。该提案旨在为节能CMP系统构建一个框架，使系统架构师能够以系统的方式做出各种与电源相关的决策，从关闭和减速状态的选择到速度缩放和负载平衡的架构支持。该方法依赖于制定的速度缩放问题及其在各种约束下的不同情况下作为一个优化问题。优化问题不仅考虑封装效应，而且考虑整个CMP芯片的散热空间分布。特别注意泄漏功率，鉴于其由于先进的工艺、低电压（例如，亚阈值）电路操作以及由于不受关断或减速措施影响的块所引起的“架构泄漏”。泄漏的PI处理基于两个关键概念：提供最佳能效处理的临界速度的高效运行时确定;以及采用系统级功耗的全局视图并利用灵活性进行功率状态改变以实现有效负载平衡和延迟隐藏效果的调度方法。PI还试图通过使应用开发者能够使用功率感知API（例如，其可以基于当前能量可用性简档来改变算法、精度）显式地编程重要的应用特定“元数据”来捕获应用意图。该项目的智力价值在于优化技术，该技术寻求多个减速和关闭状态的明智平衡，以最有效地利用能源，同时推动物理放置和封装限制所支持的热极限。拟议的研究的更广泛的影响是其贡献的各种课程和项目的基础设施相关的热感知节能嵌入式处理的主题。该项目旨在为学生提供学习和实验操作系统内部，内存接口和时间限制计算的机会。