Modeling and Optimization of Thermal and Energy Efficient Processing in Multi-Core System-Chips

提案ID：0702792标题：建模和优化多核系统中的热和能源效率处理-芯片PI名称：Rajesh GuptaPI Inst：UC Sandiego多核系统-芯片，或芯片多处理器(CMPS)，对于新一代计算机系统架构师和实现者来说，既是机遇，也是挑战。然而，由于集成芯片的散热能力缺乏可伸缩性，以节能方式开发额外的处理资源是一个挑战。在不同的电路、逻辑或体系结构设计级别使用最知名的低功耗设计方法不足以实现多核性能改进的潜力。相反，系统的设计必须推动热极限，以最大限度地利用可用的散热极限，无论是静态的还是动态的。该提案旨在为高能效的CMP系统建立一个框架，使系统架构师能够以系统的方式作出各种与电力有关的决定，从选择关闭和减速状态到对速度调整和负载平衡的架构支持。该方法依赖于将速度缩放问题及其在各种约束下的不同实例表示为优化问题。该优化问题不仅考虑了封装效应，还考虑了化学机械抛光芯片中散热的空间分布。由于工艺的进步、低电压(例如亚阈值)电路操作以及不受停机或减速措施影响的模块所造成的“建筑泄漏”，漏电功率日益重要，因此尤其受到关注。PI对泄漏的处理基于两个关键概念：提供最佳能效处理的关键速度的高效运行时间确定；以及全局查看系统级功耗并利用灵活性进行电源状态更改以实现有效的负载平衡和延迟隐藏效果的调度方法。PI还试图通过使应用程序开发者能够使用功率感知API(例如，其可能改变算法、基于当前能量可用性配置文件的精度)来显式地编程重要的特定于应用程序的‘元数据’来捕捉应用程序意图。该项目的智能优点在于优化技术，该技术寻求多种减速和关闭状态的明智平衡，以最有效地利用能源，同时提高物理布局和包装限制所支持的热极限。拟议研究的更广泛影响是它对与热感知节能嵌入式处理主题相关的各种课程和项目的基础设施的贡献。该项目旨在为学生提供学习和试验操作系统内部结构、内存接口和限时计算的机会。

Proposal ID: 0702792Title: Modeling and Optimization of Thermal and Energy Efficient Processing in Multi-Core System-ChipsPI name: Rajesh GuptaPI Inst: UC SanDiego Multi-Core System-Chips, or Chip Multi Processors (CMPs), represent both an opportunity as well as a challenge to the new generation of computer system architects and implementers. However, the exploitation of additional processing resources in an energy efficient manner is a challenge due to lack of scalability of the heat dissipation capabilities of the integrated chips. Use of best known methods for low power design at various circuit, logic or architectural design levels is not enough to realize the potential for multi-core performance improvement. Instead, systems must be architected to push the thermal limits to take the maximum advantage of the available heat dissipation limits, both statically as well as dynamically. This proposal seeks to build a framework for energy-efficient CMP systems that enables the system architect to make various power related decisions from the choice of shutdown and slowdown states to architectural support for speed scaling and load balancing -- in a systematic manner. The approach relies upon the formulation of the speed scaling problem and its different instances under various constraints as an optimization problem. The optimization problem takes into account not only package effects, but also spatial distribution of heat dissipation across the CMP die. Particular attention is paid to leakage power, given its growing importance due to the advancing processes, low voltage (e.g., sub-threshold) circuit operations and due to 'architectural leakage' caused by blocks that are not subject to shutdown or slowdown measures. The PIs treatment of leakage is based on two key concepts: efficient runtime determination of a critical speed that provides optimum energy efficient processing; and scheduling methods that takes a global view of the system level power consumption and exploit the flexibility to make power state changes to achieve effective load-balancing and latency hiding effects. The PI also seek to capture the application intent by enabling the application developer to explicitly program important application-specific 'metadata' using a power-aware API (that, for instance, may change algorithms, precision based on current energy availability profile). The intellectual merit of the project is in optimization techniques that seek a judicious balance of multiple slowdown and shutdown states for the most efficient utilization of energy while pushing the thermal limits supported by the physical placement and packaging constraints. The broader impact of the proposed research is its contribution to an infrastructure of various courses and projects related to the topic of thermally aware energy efficient embedded processing. The project seeks to provide students chance to learn and experiment with the OS internals, memory interfaces and time-bound computations.