Computer-Aided Design Tools for Asynchronous Circuits

这项研究是关于异步电路综合和验证方法的发展。该方法是将已成功应用于速度无关电路的状态探测的近似技术扩展到半定制定时电路。正在开发的工具和技术包括：1.在体系结构、门和电路级对电路面积、性能和功率的估计器；2.接受行为规范并导出门级电路的综合工具；以及3.用于定时电路的分层验证工具。集成了验证和综合工具，以支持高级逻辑优化。

This research is on the development of methods for synthesis and verification of asynchronous circuits. The approach is to extend approximation techniques for state exploration, that have been successfully applied to speed-independent circuits, to semi-custom timed circuits. Tools and techniques being developed include: 1. estimators of circuit area, performance, and power at architectural, gate, and circuit levels; 2. a synthesis tool that accepts behavioral specifications and derives gate-level circuits; and 3. a hierarchical verification tool for timed circuits. The verification and synthesis tools are integrated so as to support advanced logic optimizations.