Computer-Aided Design Tools for Asynchronous Circuits

本研究旨在发展异步电路的综合与验证方法。 该方法是扩展近似技术的状态探索，已成功地应用于速度无关的电路，半自定义定时电路。 正在开发的工具和技术包括：1。 电路面积，性能和功耗在架构，门和电路水平的估计; 2.接受行为规范并导出门级电路的合成工具;以及3.一种用于定时电路的分层验证工具。 验证和综合工具集成，以支持先进的逻辑优化。

This research is on the development of methods for synthesis and verification of asynchronous circuits. The approach is to extend approximation techniques for state exploration, that have been successfully applied to speed-independent circuits, to semi-custom timed circuits. Tools and techniques being developed include: 1. estimators of circuit area, performance, and power at architectural, gate, and circuit levels; 2. a synthesis tool that accepts behavioral specifications and derives gate-level circuits; and 3. a hierarchical verification tool for timed circuits. The verification and synthesis tools are integrated so as to support advanced logic optimizations.