SHF: Small: Methodology, Tools, and Circuits for Bundled-Data Resilient Asynchronous Design

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The impact of this research will span both academia and industry, yielding: (1) fundamental theory to design and analyze asynchronous circuits that gracefully adapt to process variability and makes near-threshold (i.e., low-power) computing practical; (2) a CAD flow that makes asynchronous circuits far more attractive for the ultra-low-power market. The research is coupled with a comprehensive plan to foster innovation in engineering, including plans for commercializing this research. The plans also include student training and future workforce development for the electronic chip industry.The unrelenting demand for longer battery life and energy-efficient designs is increasing the desire for integrated chip voltage supplies to go lower and lower, approaching near threshold levels. This aggravates process variability which forces increasing margins in traditional synchronous clock periods, yielding far-from-optimal solutions. The focus of this proposal is a recently proposed new resilient asynchronous design style, called the "Blade", that is robust to meta-stability, robust to hold times, and architecturally agnostic, not relying on architectural replay to correct for errors. This proposal will create a comprehensive framework to support the efficient design of Blade circuits with emphasis on test, synthesis, and physical design.