SHF: Small: Reconditioning: Optimizing Conditional Communication in Asynchronous Design

该提案解决了降低数字电子电路功耗的巨大挑战，利用了一个有前途的新的异步电路自动化设计流程。这种新颖的流程主动管理电路中的数据流，并且能够禁用计算块，否则将执行不必要的计算并浪费功率。提出的研究是开发数学软件算法，将优化电路划分为计算块，以最大限度地减少被禁用的块，从而最大限度地减少功耗。这项研究的影响将跨越工程、科学和社会价值。首先，它将使合成异步设计更低功耗、更快，从而更引人注目。此外，由于该研究基于通信过程的正式框架，因此通常适用于许多计算系统，包括下一代超越cmos的计算平台。在社会层面，它将使南加州大学和其他机构的学生更加丰富，因为工具流可以更广泛地使用。最后，它将为大学前拓展计划提供丰富的背景，在该计划中，首席研究员向高中生讲授电子工程、集成芯片设计、绿色经济和帮助形成可持续社会的世界

This proposal addresses the grand challenge of reducing power consumption of digital electronic circuits leveraging off of a promising new automated design flow for asynchronous circuits. This novel flow actively manages data-flow within the circuit and is capable of disabling computational blocks that would otherwise perform unnecessary calculations and waste power. The proposed research is to develop mathematical software algorithms that will optimize the partitioning of the circuit into computational blocks to maximize the blocks that are disabled and thereby minimize power consumption.The impact of this research will span engineering, scientific, and social values. First, it will enable synthesized asynchronous designs to be lower-power and faster and thus more compelling. Moreover, because the research is based on a formal framework of communicating processes it is generally applicable to many computational systems, including next-generation beyond-CMOS computational platforms. At the social level it will enable the enrichment of students at USC and other institutions as the tool flow is made more widely available. Lastly, it will provide a rich context for a pre-college outreach program in which the principal investigator teaches high-school students about the world of electrical engineering, integrated chip design, and in a greener economy and helping form a sustainable society