A Systematic Approach to the Design of Cost-Effective, High Performance Switching Architectures

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This proposal aims to answer a set of critical questions dealing with communication systems by way of the development and use of a simulation and implementation modeling environment for virtual circuit switches. The first question concerns systematic, standardized performance comparisons. Using relevant traffic models and trace data from actual applications, this study is standardizing performance measurements, eliminating the apples-to- oranges comparisons that result when considering performance results from different research groups. The second question concerns cost and implementation modeling. This work is integrating the design of system architecture and implementation. The particular focus is on electronic implementation and multichip module packaging technology. The third question concerns the role of architecture in providing quality of service guarantees. The usual abstraction of the switch as a queue hides too much detail about internal architecture that is relevant to traffic behavior when traversing a switch. This work is characterizing the effect on traffic of different switch architectures, and developing switch mechalisms to work in concert with other mechanisms in providing quality of service guarantees. The educational part of the project is using the simulation and implementation modeling environment as a key component of a graduate course in High Speed Switching Networks. In addition, portions of the research amp appear in two undergraduate courses, one on VLSI Design and the other on Modeling. Other education efforts include significant mentoring activity and ongoing improvement in teaching.