Functional Testing of Complex Digital Systems

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This research is on techniques for testing VLSI circuits directly at functional levels, while ensuring that standard testing quality goals are met. A high-level fault model called the induced functional fault (IF) model is being investigated. With this model, an IF fault class can be coupled to a physical fault class so that detection of IF faults ensures detection of physical faults. Advantages of this approach are easy derivation of near- minimal test sets, and reuse of tests in other circuits. The construction, use and reuse of precomputed tests for sequential circuits are being explored. In this regard, the application of balance and functional properties to simplifying test generation and improving fault coverage are being studied. Built-in self- testing methods that facilitate the implementation of functional testing methods and the detection and elimination of design errors are also being explored.