Lifetime Validation of IP-Based Systems-on-a-Chip

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Systems-on-a-chip (SOCs) contain predesigned subsystems that contain intellectual property (IP) from many sources. IP- based design technologies allow the use of predesigned subsystems, which facilitate the design of complex, critical systems. However, it introduces some fundamental problems in validation. This research is exploring methodologies for lifetime validation for ensuring that an IP based SOC operates within acceptable correctness bounds over its projected lifetime. Here, validation means the task of ensuring that a system contains no undetected design errors or physical faults that can cause a critical system failure. An integrated approach to design verification and physical fault testing for SOCs employing components, whose implementation or validation status is incompletely, known is being pursued. The research focuses on two related issues: (1) devising synthetic models of design errors that lead to high quality design validation methods; and (2) validating designs that contain IP-style circuits. Functional testing methods that provide implementation- independent fault coverage are being developed. The research includes theoretical studies and experimental work using university-industry designs, with emphasis on hard-to-detect faults and safety-critical applications.