Architectural Techniques for Inherently Lower Power Computers

这个项目主要关注功耗问题，主要是关于在CMOS微处理器中功耗的真正来源是什么，以及如何在更全球的层面上将其降至最低的根本问题。目标是开发和演示支持节能指令集体系结构(PISA)的技术。为此，本文主要完成了以下四个方面的工作：1.开发工艺独立的CMOS逻辑功耗模型和度量。2.分析当前的设计，以对现有技术的统计数据进行基准测试，并识别潜在的耗电处理器子系统。3.开发将减少这些指标的新技术。4.在一个原型CMOSPISA CPU芯片上对这些技术进行了演示。这些新技术将取代门设计级方法，但将主要集中在组织和指令集体系结构方法上，这些方法固有地具有较低的功耗要求。这项研究的最终目标是加深对功率和计算之间关系的科学理解，并开发能够广泛影响VLSI技术的持续发展及其在计算中的成功使用的技术，将两者的比例降至最低。

This project focuses on the problem of power dissipation, primarily on the fundamental issues of what are the real sources of power dissipation in CMOS microprocessors, and what can be done to minimize it at a more global level. The goal is development and demonstration of techniques that would support Power-efficient Instruction Set Architectures (PISA). For this, there are four major tasks: 1. Developing technology independ models and metrics for power dissipation in CMOS logic. 2. Analyzing current day designs to benchmark the stat of the art and to indentify processor subsystems that are potential power hogs. 3. Development of new techniques that will reduce these metrics. 4. Demonstration of these techniques in a prototype CMOS PISA CPU chip. These new techniqujes will indlude gate disign level approaches, but will focus primarily on organizaitonal and instruction set architectural appropaches that inherently have a lower power requirement. The end goal of this research is to develop a deeper scientific understanding of the relationship between power and computation, and develop techniques that minimize the ratio of the two in ways that can broadly impact the continuing evolution of VLSI technology and its successful use in computing.