Architectural Techniques for Inherently Lower Power Computers

本项目关注的是功耗问题，主要是CMOS微处理器功耗的真正来源，以及如何在全球范围内将其最小化的基本问题。目标是开发和演示支持高效能指令集架构（PISA）的技术。为此，有四个主要任务：1。开发CMOS逻辑中与技术无关的功耗模型和指标。2. 分析当前的设计，以对技术状态进行基准测试，并确定潜在的功耗消耗者处理器子系统。3. 开发可以减少这些指标的新技术。4. 这些技术的示范在一个原型CMOS比萨CPU芯片。这些新技术将包括栅极设计级方法，但将主要关注具有较低功耗要求的组织和指令集架构方法。本研究的最终目标是对功率和计算之间的关系进行更深入的科学理解，并开发能够以广泛影响超大规模集成电路技术持续发展及其在计算中的成功应用的方式将两者的比例降至最低的技术。

This project focuses on the problem of power dissipation, primarily on the fundamental issues of what are the real sources of power dissipation in CMOS microprocessors, and what can be done to minimize it at a more global level. The goal is development and demonstration of techniques that would support Power-efficient Instruction Set Architectures (PISA). For this, there are four major tasks: 1. Developing technology independ models and metrics for power dissipation in CMOS logic. 2. Analyzing current day designs to benchmark the stat of the art and to indentify processor subsystems that are potential power hogs. 3. Development of new techniques that will reduce these metrics. 4. Demonstration of these techniques in a prototype CMOS PISA CPU chip. These new techniqujes will indlude gate disign level approaches, but will focus primarily on organizaitonal and instruction set architectural appropaches that inherently have a lower power requirement. The end goal of this research is to develop a deeper scientific understanding of the relationship between power and computation, and develop techniques that minimize the ratio of the two in ways that can broadly impact the continuing evolution of VLSI technology and its successful use in computing.