Architectural Techniques for Inherently Lower Power Computers

这个项目的重点是功耗的问题，主要是在CMOS微处理器中的功耗的真实的来源是什么，以及可以做些什么，以尽量减少它在一个更全球性的水平上的基本问题。 目标是开发和演示支持高能效指令集架构（比萨）的技术。 为此，有四项主要任务： 1. 开发独立于技术的电力模型和指标 CMOS逻辑中的耗散。 2. 分析当今设计以衡量艺术水平 并识别作为潜在电源的处理器子系统 猪。 3. 开发新技术，减少这些指标。 4. 这些技术在CMOS比萨CPU原型中的演示 芯片 这些新技术将包括门级设计方法，但主要集中在组织和指令集架构方法，固有的低功耗要求。 这项研究的最终目标是对功耗和计算之间的关系有更深入的科学理解，并开发技术，以最大限度地减少两者的比例，从而广泛影响VLSI技术的持续发展及其在计算中的成功应用。

This project focuses on the problem of power dissipation, primarily on the fundamental issues of what are the real sources of power dissipation in CMOS microprocessors, and what can be done to minimize it at a more global level. The goal is development and demonstration of techniques that would support Power-efficient Instruction Set Architectures (PISA). For this, there are four major tasks: 1. Developing technology independ models and metrics for power dissipation in CMOS logic. 2. Analyzing current day designs to benchmark the stat of the art and to indentify processor subsystems that are potential power hogs. 3. Development of new techniques that will reduce these metrics. 4. Demonstration of these techniques in a prototype CMOS PISA CPU chip. These new techniqujes will indlude gate disign level approaches, but will focus primarily on organizaitonal and instruction set architectural appropaches that inherently have a lower power requirement. The end goal of this research is to develop a deeper scientific understanding of the relationship between power and computation, and develop techniques that minimize the ratio of the two in ways that can broadly impact the continuing evolution of VLSI technology and its successful use in computing.