PDS: Pursuing a Petaflop: Point Designs for 100TF Computers Using PIM Technologies

目前的高性能计算技术存在两个主要问题。首先，最高端机器的成本远远超出了广泛部署的可行性，其次（也是更关键的）这些机器的软件环境充其量是尴尬的，并且只能勉强维持硬件能够提供的性能的一小部分。本文的论点是，大部分问题源于我们历史上对内存和CPU逻辑部分的分离。单个CPU时钟速率和内部架构继续加速，因此需要内存子系统不断增加的带宽量。这些速率远远超过了我们最密集的DRAM内存部件的带宽能力（需要控制系统成本），并且差距将随着时间的推移而扩大。最终的结果是复杂的内存层次结构，这反过来又增加了有效处理这些层次结构的成本和软件复杂性。一项新技术正在出现，以克服这一根本缺陷：在一个芯片上结合密集的DRAM和非常大量的逻辑。这种功能允许称为内存中处理（Processing-In-Memory， PIM）的新体系结构将计算放在内存宏旁边，甚至在内存宏内部，这些地方有大量的原始带宽。第一个这样的芯片EXECUBE集成在一个4Mbit DRAM芯片上，8个完整的cpu配置在一个3D二进制超立方体中，能够作为一个芯片类型的构建块用于MIMD和SIMD组织的mpp。该项目的目标是在未来十年内利用PIM技术的潜力，并证明它们承诺有效的解决方案。要使用的方法包括配置和研究一些具有100兆（fl）op潜力的“点设计”mpp，用于几个有趣的问题类别，然后利用这些架构的新特性，以及匹配的系统软件和软件开发工具，以一种不仅可以实现卓越性能，而且可以大大简化编程环境的方式来攻击它们。

There are two major problems with the current state of the art in high-performance computing. First, the cost of the very highest end machines lies far beyond the point where widespread deployment is feasible, and second (and more critical) the software environments for these machines are awkward at best, and capable of eking out only fractions of the performance that the hardware is capable of supplying. The thesis of this is that much of the problem stems from our historical separation of memory and CPU logic parts. Individual CPU clock rates and internal architectures continue to accelerate, and thus require ever increasing amounts of bandwidth from the memory subsystem. These rates have far exceeded the bandwidth capabilities of our densest DRAM memory parts (needed to control system costs), and the gap will widen over time. The net effect is complex memory hierarchies, which in turn drives cost and software complexity in addressing these hierarchies efficiently. A new technology is emerging to counter this fundamental defect: the combination on one chip of both dense DRAM and very significant amounts of logic. This capability permits new architectures termed Processing-In-Memory (PIM) to place computing either right next to, or even inside of, the memory macros, where there are huge amounts of raw bandwidth. The first such chip, EXECUBE, integrated onto a 4Mbit DRAM chip 8 complete CPUs configured in a 3D binary hypercube, and was capable of being used as a one chip-type building block for MPPs of both MIMD and SIMD organization. The objective of this project is to look at utilizing PIM technology potentials over the next decade and demonstrate that they promise efficient solution. The approach to be used involves configuring and studying some "point design" MPPs with 100 tera(fl)op potential for several interesting classes of problems, and then utilizing the novel features of these architectures, along with matching system software and software development tools, to attack them in ways that may permit not only exceptional performance, but also greatly simplified programming environments.