Advances in Register Allocation and Efficient Run-Time Program Analysis

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This project deals with register optimization techniques for modern computer architectures. In modern pipelined architectures code is carefully scheduled to avoid unnecessary delays. However, some delay slots may be unavoidable. This project will develop techniques to `glean` unfilled delay slots to perform work normally considered not worthwhile, such as splitting live ranges into shorter ranges. Shorter ranges induce fewer register conflicts, allowing registers to be used for other purposes. Normally,registers are not used across procedure boundaries. The project will develop techniques to optimally allocate registers at the interprocedural level. More specifically, the techniques will attempt to avoid unnecessary register spilling on caller/callee boundaries. The project will also investigate the use of idle processors to perform a variety of program correctness analyses. This is achieved using a `shadow` process which executes only when a processor becomes idle.