Micromechanical Study of Failure in Narrow Interconnect Lines

Cuitino半导体的设计，例如静态和动态随机存取存储器，使用薄的金属互连线。 预计未来的器件将使用更薄的互连。 研究了晶粒取向差、晶粒尺寸分布、晶粒形貌、微缺陷的尺寸和形貌等微结构特征以及沉积温度、使用温度、电流密度等因素对窄互连线中空洞成核和生长的影响。 基于位错力学的晶体蠕变理论被用作本研究的中心工具。 该研究也将适用于其他领域，如单晶螺旋桨，涡轮机叶片等的设计和制造。

9610536 Cuitino Semiconductor devises, such as static and dynamic random access memory, use thin metal interconnect lines. Future devices are anticipated to use even thinner interconnects. The effect of microstructural features, such as grain misorientation, grain size distribution, grain morphology, size and morphology of microdefects, as well as of other factors including, deposition temperature, usage temperature, electric current density, on nucleation and growth of voids in narrow interconnects is studies. crystal creep theory based on dislocation mechanics is employed as the central tool for this investigation. The study will also be applicable in other areas such as the design and fabrication of single crystal propellers, turbine blades, etc. ***