Decoupling and Reforming Tag and Data Arrays for High-Performance Memory Hierarchy Systems

该项目研究了内存层次设计中的问题，并提出了解决方案，以弥合处理器和内存之间日益增长的性能差距。 通过观察执行高速缓存标签访问/比较和访问高速缓存数据所需的不相等时间，可以利用这种路径不平衡来实现性能更优的高速缓存设计。 其基本思想是使用一个附加的标记数组来记录该高速缓存数据数组中最近使用的行的状态和位置。 通过在标记阵列的该子集中记录该高速缓存线位置，数据访问与标记访问/比较路径解耦，从而缩短了总的高速缓存访问时间。 在多处理器系统中，高速缓存一致性活动会给负载沉重的监听总线带来额外的流量，并在访问数据时造成额外的延迟。 通过观察到对相同存储器位置的引用通常在软件级别排序，频繁渲染高速缓存一致性活动是不必要的，并且可以推迟到适当的同步点。 所需的基础设施，包括一个多处理器跟踪设施，多问题的顺序执行处理器模型，和各种内存层次模型，将在这个项目中开发。 这些工具将通过图形用户界面得到增强，并用于教学目的，为学生提供评估不同架构设计权衡的实践经验。

The project investigates issues in memory hierarchy design and proposes solutions to bridge the increasing performance gap between the processor and memory. By observing the unequal time needed to perform cache tag access/comparison and to access cache data, this path imbalance can be exploited to achieve a more performance optimal cache design. The basic idea is to use an additional tag array record the status and location of the recently used lines in the cache data array. By recording the cache line locations in this subset of the tag array, the data access is decoupled from the tag access/comparison path for a shorter overall cache access time. In a multiprocessor system, cache coherence activities incur extra traffic to the heavily-loaded snooping bus and impose additional latency in accessing the data. By observing that references to the same memory location are often ordered at the software level, frequently rendering cache coherence activities are unnecessary and can be deferred until at the proper synchronization point. The infrastructure required, including a multiprocessor tracing facility, multiple-issue out-of-order execution processor models, and various memory hierarchy models, will be developed in this project. These tools will be enhanced with graphical user interfaces and used for instructional purposes to provide students with hands-on experience in evaluating difference architectural design tradeoffs.