Predictive Multiprocessor Caching Techniques Based on Cache Interference and Working Set Change

这个项目的目标是调查和评估基于硬件的创新方法，以减少由于干扰而导致的多处理器高速缓存中的未命中。多处理器中的高速缓存线之间的干扰可能会导致线在它们仍在计算的工作集中时被不由自主地放弃。本研究的基本思想是记录缓存非自愿放弃的行，并将其作为预取目标。将进行基于事务处理和科学工作负载的模拟研究，以评估几种预取选择算法。这些算法包括利用一致性事务的直观方法，以及更激进的方法，其中修改高速缓存线的进程通知其他进程预取该线。

The objective of this project is to investigate and evaluate innovative hardware-based approaches to reducing misses in multiprocessor caches due to interference. Interference between cache lines in a multiprocessor can cause lines to be involuntarily relinquished while they are still in the working set of a computation. The problem is especially serious for modified lines, which not only account for a large percentage of cache misses, but also incur a high miss penalty.The fundamental idea in this research is to record the lines that a cache has given up involuntarily, and use them as prefetching targets. Simulation studies based on transaction processing and scientific workloads will be carried out to evaluate several algorithms for prefetch selection. These algorithms include intuitive approaches that take advantage of coherence transactions, as well as more aggressive approaches in which processes that modify a cache line notify other processes to prefetch that line.