Predictive Multiprocessor Caching Techniques Based on Cache Interference and Working Set Change

基于缓存干扰和工作集变化的预测性多处理器缓存技术

• 批准号: 0073473
• 负责人: Jih-Kwon Peir
• 金额: --
• 依托单位: University of Florida
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2000
• 资助国家: 美国
• 起止时间: 2000-07-15 至 2004-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0073473&HistoricalAwards=false
• 关键词: Predictive; Multiprocessor; Caching; Techniques; Based

The objective of this project is to investigate and evaluate innovative hardware-based approaches to reducing misses in multiprocessor caches due to interference. Interference between cache lines in a multiprocessor can cause lines to be involuntarily relinquished while they are still in the working set of a computation. The problem is especially serious for modified lines, which not only account for a large percentage of cache misses, but also incur a high miss penalty.The fundamental idea in this research is to record the lines that a cache has given up involuntarily, and use them as prefetching targets. Simulation studies based on transaction processing and scientific workloads will be carried out to evaluate several algorithms for prefetch selection. These algorithms include intuitive approaches that take advantage of coherence transactions, as well as more aggressive approaches in which processes that modify a cache line notify other processes to prefetch that line.

这个项目的目的是调查和评估创新的基于硬件的方法，以减少在多处理器缓存由于干扰的失误。 多处理器中高速缓存行之间的干扰会导致行在仍处于计算的工作集中时被非自愿地放弃。 修改行的问题尤其严重，它不仅占了很大比例的高速缓存未命中，而且还招致了高miss penalty.本研究的基本思想是记录的高速缓存已经放弃了非自愿的行，并使用它们作为预取目标。 基于事务处理和科学工作量的模拟研究将进行评估预取选择的几种算法。 这些算法包括利用一致性事务的直观方法，以及更积极的方法，其中修改高速缓存行的进程通知其他进程预取该行。