Development of an Undergraduate VLSI Test Laboratory for Digital, Analog and Mixed-Signal Circuits
Development of an Undergraduate VLSI Test Laboratory for Digital, Analog and Mixed-Signal Circuits
批准号:
9650672
负责人:
Ramalingam Sridhar
金额:
$3.9万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
1996
资助国家:
美国
项目状态:
已结题
起止时间:
1996-07-01 至 1999-06-30
中文摘要
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英文摘要
The purpose of this project is the development of an undergraduate VLSI laboratory for testing digital, analog, and mixed-signal circuits. The lab includes an integrated test platform based on a CMT Mixed-Signal Test Station and a high-speed oscilloscope. The laboratory is intended to supplement two existing undergraduate courses, Introduction to VLSI Electronics and VLSI Testing, and to provide much needed hands-on experience for the undergraduate students. This process will enable the undergraduate students to take a mixed-signal VLSI circuit design from initial specifications to a working implementation. The skyrocketing demands for mixed-signal technology in telecommunication, high-performance computing, and automotive electronics have necessitated the introduction of this technology at the undergraduate level. Rapid prototyping with the help of automated design and test tools is perceived as the most appropriate method of providing the students with a clear concept of the various steps in the design, debugging, and evaluation of a typical VLSI system. A new course focusing on the advanced design issues of analog and mixed-signal circuits in VLSI is to be offered, fully utilizing the new laboratory. The upgrading of the existing courses provides the ABET-recommended major meaningful design experience (MMDE) in the VLSI track of the undergraduate curriculum. This new laboratory is expected to have a direct impact on about two-thirds of the undergraduate ECE students. The project's practical experiences can enhance the job opportunities for the students in leading industries, where such skills are of great value.
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RIA: High-Performance VLSI Systems Using CMOS Wave- Pipelined Transmission Gate Logic
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批准号:9409762
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项目类别:Standard Grant
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资助金额:$9.74万
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财政年份:1994
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负责人:Ramalingam Sridhar
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依托单位:
海外基金