RIA: High-Performance VLSI Systems Using CMOS Wave- Pipelined Transmission Gate Logic

RIA：使用 CMOS 波流水线传输门逻辑的高性能 VLSI 系统

• 批准号: 9409762
• 负责人: Ramalingam Sridhar
• 金额: $ 9.74万
• 依托单位: SUNY at Buffalo
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1994
• 资助国家: 美国
• 起止时间: 1994-08-01 至 1998-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9409762&HistoricalAwards=false
• 关键词: RIA; Performance; VLSI; Systems; Using

Wave pipelining eliminates the intermediate register stages in a pipelined system by using the internal capacitance of the combinational logic for temporary storage. to obtain a high operating speed, equal path delays must be ensured between all the input and the output nodes of a given functional block. This requires symmetric rise and fall times, and delay independence on the input patterns for each component within the functional unit. This project proposes a method that uses a modified complementary Pass-transistor Logic (CPL) circuits as the basic cells to implement a high performance CMOS wave-pipelined system. Preliminary research and design results show that the family of basic cells, called Wave-pipelined Transmission-Gate Logic (WTGI), using standard CMOS technology, can be designed to have equal rise/fall times and reduced gate delay variations as compared to other approaches. The project addresses the design of a WTGL cell library for computational and signal processing applications. Further, logic synthesis and the delay tuning algorithms will be developed with an emphasis towards an application i signal processing. CAD tools that can effectively use the WRGL technique will be developed.

波流水线通过使用组合逻辑的内部电容进行临时存储来消除流水线系统中的中间寄存器级。 为了获得高的操作速度，必须在给定功能块的所有输入和输出节点之间确保相等的路径延迟。 这需要对称的上升和下降时间，以及对功能单元内每个组件的输入模式的延迟独立性。 本计画提出一种以互补式传输晶体管逻辑（CPL）电路为基本单元，以实现高效能CMOS波形管线系统的方法。 初步的研究和设计结果表明，家庭的基本单元，称为波流水线传输门逻辑（WTGI），使用标准的CMOS技术，可以被设计为具有相等的上升/下降时间和减少门延迟的变化相比，其他方法。 该项目解决了计算和信号处理应用程序的WTGL细胞库的设计。 此外，逻辑综合和延迟调谐算法将发展的重点是在信号处理中的应用。 将开发能够有效使用WRGL技术的CAD工具。