Optimized Testable Synthesis of Sequential Circuits

本研究旨在开发可测试数字顺序电路的合成算法和工具。可测试综合问题过去被视为两个独立的问题，即状态分配问题和测试问题。算法和工具可以综合区域效率和可测试的设计顺序电路表示为有限状态机正在开发。正在探索使用CAD工具和/或本项目中开发的测试体系结构划分和重新合成大型顺序电路的方法，以及为结果电路生成测试向量的方法。

This research is on developing algorithms and tools to synthesize testable digital sequential circuits. The testable synthesis problem has in the past been dealt with as two independent problems namely, the state assignment problem and the testing problem. Algorithms and tools that can synthesize area-efficient and testable designs of sequential circuits represented as finite state machines are being developed. Methods of partitioning and re-synthesizing large sequential circuits using the CAD tools and/or the test architectures developed in this project and generation of test vectors for the resulting circuits are being explored.