Optimized Testable Synthesis of Sequential Circuits

时序电路的优化可测试综合

• 批准号: 9714034
• 负责人: Kewal Saluja
• 金额: $ 19.6万
• 依托单位: University of Wisconsin-Madison
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1997
• 资助国家: 美国
• 起止时间: 1997-12-01 至 2001-11-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9714034&HistoricalAwards=false
• 关键词: Optimized; Testable; Synthesis; Sequential; Circuits

This research is on developing algorithms and tools to synthesize testable digital sequential circuits. The testable synthesis problem has in the past been dealt with as two independent problems namely, the state assignment problem and the testing problem. Algorithms and tools that can synthesize area-efficient and testable designs of sequential circuits represented as finite state machines are being developed. Methods of partitioning and re-synthesizing large sequential circuits using the CAD tools and/or the test architectures developed in this project and generation of test vectors for the resulting circuits are being explored.

本研究旨在发展可测试数位时序电路的综合演算法与工具。可测试综合问题在过去一直被视为两个独立的问题，即状态分配问题和测试问题。正在开发的算法和工具，可以综合面积效率和可测试的设计表示为有限状态机的时序电路。正在探索使用CAD工具和/或在这个项目中开发的测试架构和产生的电路测试向量的分区和重新合成大型时序电路的方法。