CISE Research Instrumentation: Infrastructure to Support Accurate Performance Measurements of Multithreaded Programs

9729889 Cohen，William E. 克里希纳·卡维亚拉巴马大学亨茨维尔分校 CISE研究仪器：支持多线程程序精确性能测量的基础设施 该研究仪器使以下研究项目成为可能： - 预加载/后存储（PL/PS）体系结构，-多线程应用程序的细粒度调度，以及 - Java语言的性能评估。 为了支持上述项目，位于亨茨维尔的亚拉巴马大学（UAH）将购买一个4处理器SMP系统和数据记录硬件（NIST MultiKron II仪器板），这将为计算机和信息科学与工程的实验研究提供一个环境。 该系统的低开销的硬件/软件仪器，使多线程软件和多线程架构的准确性能测量，而不诉诸缓慢，往往是侵入性的，软件模拟技术。 该仪器支持的研究主题包括预加载/后存储（PL/PS）体系结构的评估，自适应和静态细粒度任务调度技术的比较，以及多线程Java程序的运行时性能的检查。PL/PS架构将程序中的每个任务分为三个阶段：加载、计算和存储。 将每个任务的阶段分开允许在调度代码时有更大的灵活性，并提供了隐藏内存和通信延迟的方法。 详细的模拟器和编译器优化正在开发的架构。细粒度调度检查的开销引入当代硬件/软件环境的各种调度技术应用于套件的现实世界的问题。 Java性能评估 研究Java作为高性能计算编程语言的可行性，并确定语言中限制性能的功能。 对这些主题有更好的理解将有助于提高多线程程序和体系结构的性能。

9729889 Cohen, William E. Kavi, Krishna The University of Alabama at Huntsville CISE Research Instrumentation: Infrastructure to Support Accurate Performance Measurements of Multithreaded Programs This research instrumentation enables the following research projects: - Pre-Load/Post-Store (PL/PS) architecture, - Fine-grained scheduling of multithreaded applications, and - Performance evaluation of the Java language. To support the aforementioned projects, the University of Alabama at Huntsville (UAH) will purchase a 4-processor SMP system and data logging hardware (NIST MultiKron II instrumentation board) which will provide an environment for experimental research in Computer and Information Science and Engineering. The system's low-overhead hardware/software instrumentation enables accurate performance measurements of multithreaded software and multithreaded architectures without resorting to slow, often intrusive, software simulation techniques. Research topics supported by this instrumentation include the evaluation of the Pre-Load/Post-Store (PL/PS) architecture, the comparison of adaptive and static fine-grained task scheduling techniques, and the examination of runtime performance of multithreaded Java programs. The PL/PS architecture breaks each task in a program into three phases: load, compute, and store. Separating the phases of each task allows greater flexiblity in scheduling the code and provides a means of hiding memory and communication latencies. Detailed simulators and compiler optimizations are being developed for the architecture. The fine-grained scheduling examines the overhead introduced on contemporary hardware/software environments by the various scheduling techniques applied to suites of real-world problems. The Java performance evaluation investigates the viability of Java as a programming language for high-performance computing and identifies features in the languages that limit performance. A better understanding of these topics will lead to techniques to improve the performance of multithreaded programs and architectures.