CAREER: Software Synthesis for Real-time Signal Processing Systems

数字信号处理（DSP）系统的设计人员面临的一个主要挑战是，如何获得足够高效和可预测的软件实现，其复杂性正在迅速增加。在面向消费者的应用领域，如无线通信和PC多媒体，竞争激烈的上市时间压力，以及不断升级的应用程序和处理器架构的复杂性，要求公司为软件开发维持巨大的人力资源支出。同样，在雷达信号处理等高性能应用中，如何有效地利用大规模多处理器计算机系统来划分程序和管理处理器间通信仍然是一个重大挑战。在过去的几年里，数据流是计算机辅助DSP系统设计工具中一个很有吸引力的编程模型，这一点已经得到了广泛的认识。该项目正在研究自动或交互地将DSP的高级数据流程序映射到有效软件实现的算法。具体而言，本研究正在探索(1)数据流编程和命令式编程格式的彻底集成，以及数据流编译技术与现有命令式语言编译技术的有效集成；(2)开发用于将数据流模型映射到多处理器架构上的实现的自动和交互式软件工具，重点是有效管理调度、处理器间通信和同步之间的交互；(3)开发将数据流计算模型编译成单处理器实现的算法，使程序和数据内存需求、各个子程序的调用开销以及延迟得到优化。

A major challenge facing designers for digital signal processing (DSP) systems is the rapidly increasing complexity of deriving sufficiently efficient and predictable software implementations. In consumer-oriented application domains such as wireless communications and PC multimedia, extremely competitive time-to- market pressure together with the continually escalating complexity of applications and processor architectures require companies to sustain enormous human resource expenditures for software development. Similarly, in very high performance applications such as radar signal processing, it remains a significant challenge to partition programs and manage interprocessor communication in a manner that effectively exploits large-scale multiprocessor computer systems. Over the past several years, it has become widely recognized that dataflow is an attractive programming model for computer-aided DSP system design tools. This project is investigating algorithms that automatically or interactively map high-level, dataflow programs for DSP into efficient software implementations. Specifically, this research is exploring (1) a thorough integration of dataflow programming and imperative programming formats, and an efficient integration of techniques for compiling dataflow with the existing techniques for compiling imperative languages; (2) the development of automatic and interactive software tools for mapping dataflow models into implementations on multiprocessor architectures, with emphasis on efficiently managing the interactions between scheduling, interprocessor communication, and synchronization; and (3) the development of algorithms for compiling dataflow computations models into uniprocessor implementations in such a way that program and data memory requirements, invocation overhead of individual subprograms, and latency are optimized.