CAREER: Software Synthesis for Real-time Signal Processing Systems

职业：实时信号处理系统的软件综合

• 批准号: 9734275
• 负责人: Shuvra Shikhar Bhattacharyya
• 金额: $ 20万
• 依托单位: University of Maryland, College Park
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1998
• 资助国家: 美国
• 起止时间: 1998-01-15 至 2003-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9734275&HistoricalAwards=false
• 关键词: CAREER; Software; Synthesis; Real; time

A major challenge facing designers for digital signal processing (DSP) systems is the rapidly increasing complexity of deriving sufficiently efficient and predictable software implementations. In consumer-oriented application domains such as wireless communications and PC multimedia, extremely competitive time-to- market pressure together with the continually escalating complexity of applications and processor architectures require companies to sustain enormous human resource expenditures for software development. Similarly, in very high performance applications such as radar signal processing, it remains a significant challenge to partition programs and manage interprocessor communication in a manner that effectively exploits large-scale multiprocessor computer systems. Over the past several years, it has become widely recognized that dataflow is an attractive programming model for computer-aided DSP system design tools. This project is investigating algorithms that automatically or interactively map high-level, dataflow programs for DSP into efficient software implementations. Specifically, this research is exploring (1) a thorough integration of dataflow programming and imperative programming formats, and an efficient integration of techniques for compiling dataflow with the existing techniques for compiling imperative languages; (2) the development of automatic and interactive software tools for mapping dataflow models into implementations on multiprocessor architectures, with emphasis on efficiently managing the interactions between scheduling, interprocessor communication, and synchronization; and (3) the development of algorithms for compiling dataflow computations models into uniprocessor implementations in such a way that program and data memory requirements, invocation overhead of individual subprograms, and latency are optimized.

数字信号处理（DSP）系统设计者面临的一个主要挑战是快速增加获得足够有效和可预测的软件实现的复杂性。 在面向消费者的应用领域，如无线通信和PC多媒体，极具竞争力的上市时间的压力，以及不断升级的应用程序和处理器架构的复杂性，要求公司维持巨大的人力资源支出的软件开发。 类似地，在诸如雷达信号处理的非常高性能的应用中，以有效地利用大规模多处理器计算机系统的方式来划分程序和管理处理器间通信仍然是一个重大的挑战。 在过去的几年里，它已成为广泛认识到，EQUALLOW是一个有吸引力的编程模型的计算机辅助DSP系统设计工具。 该项目正在研究自动或交互式地将DSP的高级、可编程的程序映射到高效的软件实现中的算法。 具体地说，本研究正在探索（1）一个彻底的集成的命令式编程和编程格式，并有效地集成的编译命令式语言与现有的编译命令式语言的技术，编译的命令式语言的技术;（2）开发自动和交互式软件工具，用于将CMDLOW模型映射到多处理器架构上的实现，重点是有效地管理调度、处理器间通信和同步之间的交互;以及（3）开发用于将并行计算模型编译成单处理器实现的算法，各个子程序的调用开销和延迟都得到了优化。