SBIR Phase II: Boundary Scan and Built-In Self Test (BIST) Insertion into VHDL Designs with Commercial Off-the-Shelf (COTS) Components or Embedded Cores

点击翻译按钮获取中文摘要

*** 9801308 Stoel This Small Business Innovation Research Phase 11 project provides a solution to deal with the negative impact that commercial off-the-shelf (COTS) components have on testability. The ever shrinking time-to-market, in the electronics industry, has created an increasing need for COTS components to slash development time. At the chip level, where Intellectual Property (IP) cores are being used, the main problem is controllability of the primary inputs and observability of the primary outputs of the embedded cores. ASC has developed a solution based on the boundary scan standard being applied to all cores. To avoid high circuitry overhead and long test times, ASC developed an optimization methodology during Phase I, which provides: Direct access to each embedded core, short test times, low hardware overhead, and flexibility in test configuration. During Phase II, ASC will enhance its existing VBIT(R) tool to allow designers to automatically insert optimized boundary scan in their chip designs with embedded cores. This new VBIT-MC (Multi-Core) tool will be integrated into existing EDA design flows, be capable of using existing test data, and have a graphical front-end. With a rapidly growing market for test tools and without competitors on the horizon, the commercial prospects for VBIT-MC are excellent. ***