SBIR Phase II: Boundary Scan and Built-In Self Test (BIST) Insertion into VHDL Designs with Commercial Off-the-Shelf (COTS) Components or Embedded Cores

SBIR 第二阶段：将边界扫描和内置自测试 (BI​​ST) 插入到具有商用现成 (COTS) 组件或嵌入式内核的 VHDL 设计中

• 批准号: 9801308
• 负责人: Alexandru N. Zamfirescu
• 金额: $ 40万
• 依托单位: ALTERNATIVE SYSTEM CONCEPTS, INC.
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1998
• 资助国家: 美国
• 起止时间: 1998-06-01 至 2000-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9801308&HistoricalAwards=false
• 关键词: SBIR; Phase; II; Boundary; Scan

*** 9801308 Stoel This Small Business Innovation Research Phase 11 project provides a solution to deal with the negative impact that commercial off-the-shelf (COTS) components have on testability. The ever shrinking time-to-market, in the electronics industry, has created an increasing need for COTS components to slash development time. At the chip level, where Intellectual Property (IP) cores are being used, the main problem is controllability of the primary inputs and observability of the primary outputs of the embedded cores. ASC has developed a solution based on the boundary scan standard being applied to all cores. To avoid high circuitry overhead and long test times, ASC developed an optimization methodology during Phase I, which provides: Direct access to each embedded core, short test times, low hardware overhead, and flexibility in test configuration. During Phase II, ASC will enhance its existing VBIT(R) tool to allow designers to automatically insert optimized boundary scan in their chip designs with embedded cores. This new VBIT-MC (Multi-Core) tool will be integrated into existing EDA design flows, be capable of using existing test data, and have a graphical front-end. With a rapidly growing market for test tools and without competitors on the horizon, the commercial prospects for VBIT-MC are excellent. ***

这个小型企业创新研究第11阶段项目提供了一个解决方案，以处理商业现货（COTS）组件对可测试性的负面影响。在电子工业中，进入市场的时间不断缩短，对COTS组件的需求不断增加，以减少开发时间。在使用知识产权（IP）内核的芯片级别，主要问题是主要输入的可控性和嵌入式内核主要输出的可观察性。ASC开发了一种基于适用于所有内核的边界扫描标准的解决方案。为了避免高电路开销和长测试时间，ASC在第一阶段开发了一种优化方法，它提供：直接访问每个嵌入式核心，短测试时间，低硬件开销，以及测试配置的灵活性。在第二阶段，ASC将增强其现有的VBIT(R)工具，使设计人员能够在嵌入内核的芯片设计中自动插入优化的边界扫描。这种新的VBIT-MC（多核）工具将集成到现有的EDA设计流程中，能够使用现有的测试数据，并具有图形前端。随着测试工具市场的快速增长和没有竞争对手的出现，VBIT-MC的商业前景非常好。＊＊＊