Computational Methods for the Simulation of Chemical Vapor Deposition on Rough Surfaces

9805547马蒂亚斯·K·戈伯特模拟粗糙表面化学气相沉积的计算方法摘要：在化学气相沉积(CVD)过程中，反应气体的混合物被施加到化学反应器反应室中半导体晶片的表面。通过与表面材料的表面反应，在表面上形成材料的薄膜。晶片表面包含用于互连线、晶体管栅极等的小沟槽和孔，统称为特征，从而使表面变得粗糙。目前，基于Navier-Stokes方程的反应器尺度模型(RSM)捕获了典型尺寸为10厘米的整个反应室内的反应气体流动，而基于动力学方程的特征尺度模型(FSM)预测了典型尺寸为1微米的单个特征内的薄膜生长轮廓。由于长度尺度的极大差异，通过引入1毫米量级的典型尺寸的介观尺度模型(MSM)，可以得到一个跨越所有长度尺度的完整过程模型。本项目将为在这种规模的低压区域建立适当的动力学方程建立数学模型和计算方法。该项目是对计算机芯片制造过程进行建模的努力的一部分。计算机已经是并将继续是我们经济和技术最重要的工具之一。有一种趋势是，更专业的计算机芯片将以较小的数量生产，例如用于太空探索或国防系统的特定应用。但测试制造过程所需的原型运行使用昂贵的化学品，并产生危险的废气，这些废气在释放到环境中之前需要经过处理。由于这些原因，人们对模拟从单个设备到车间的所有尺度的制造过程的兴趣一直在增加。该项目将有助于开发适当的模型以及更好的化学气相沉积过程的数值技术，这是计算机芯片生产的关键步骤之一。在这个过程中，一层薄薄的材料被沉积，以形成组成最终产品中的计算机芯片的电线或电子设备。

DMS 9805547 Matthias K. Gobbert Computational Methods for the Simulation of Chemical Vapor Deposition on Rough Surfaces Abstract: In chemical vapor deposition (CVD) processes a mixture of reacting gases is applied to the surface of a semiconductor wafer in the reaction chamber of a chemical reactor. A thin film of material is formed on the surface via surface reactions with the surface material. The wafer surface contains small trenches and holes, collectively referred to as features, for interconnect lines, transistor gates, etc., thus making the surface rough. Currently, reactor scale models (RSM) based on the Navier-Stokes equations capture the flow of the reacting gases throughout the entire reactor chamber with a typical dimension of 10 centimeters, and feature scale models (FSM) based on kinetic equations predict the film growth profile inside a single feature with a typical dimension of 1 micrometer. Due to the extreme difference of length scales, an integrated process model spanning all length scales of interest is best obtained by introducing a mesoscopic scale model (MSM) with typical dimension on the order of 1 millimeter. This project will develop the mathematical model and computational methods for the appropriate kinetic equations in the low pressure regime on this scale. This project is part of an effort at modeling the manufacturing processes of computer chips. Computers are already and will continue to be one of the most important tools of our economy and technology. There is a trend towards more specialized computer chips to be produced in smaller numbers, for instance for specific applications in space exploration or defense systems. But prototype runs necessary to test the manufacturing processes use expensive chemicals and produce hazardous exhaust gases, which need to be treated before releasing them to the environment. For these reasons, interest in simulating the manufacturing processes on all scales from individual device to fa ctory floor has been increasing. This project will contribute to the development of appropriate models as well as better numerical techniques for the process of chemical vapor deposition, one of the crucial production steps for computer chips. In this process, a thin layer of material is deposited to form either the electrical lines or the electronic devices that make up the computer chip in the final product.