Computational Methods for the Simulation of Chemical Vapor Deposition on Rough Surfaces

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DMS 9805547 Matthias K. Gobbert Computational Methods for the Simulation of Chemical Vapor Deposition on Rough Surfaces Abstract: In chemical vapor deposition (CVD) processes a mixture of reacting gases is applied to the surface of a semiconductor wafer in the reaction chamber of a chemical reactor. A thin film of material is formed on the surface via surface reactions with the surface material. The wafer surface contains small trenches and holes, collectively referred to as features, for interconnect lines, transistor gates, etc., thus making the surface rough. Currently, reactor scale models (RSM) based on the Navier-Stokes equations capture the flow of the reacting gases throughout the entire reactor chamber with a typical dimension of 10 centimeters, and feature scale models (FSM) based on kinetic equations predict the film growth profile inside a single feature with a typical dimension of 1 micrometer. Due to the extreme difference of length scales, an integrated process model spanning all length scales of interest is best obtained by introducing a mesoscopic scale model (MSM) with typical dimension on the order of 1 millimeter. This project will develop the mathematical model and computational methods for the appropriate kinetic equations in the low pressure regime on this scale. This project is part of an effort at modeling the manufacturing processes of computer chips. Computers are already and will continue to be one of the most important tools of our economy and technology. There is a trend towards more specialized computer chips to be produced in smaller numbers, for instance for specific applications in space exploration or defense systems. But prototype runs necessary to test the manufacturing processes use expensive chemicals and produce hazardous exhaust gases, which need to be treated before releasing them to the environment. For these reasons, interest in simulating the manufacturing processes on all scales from individual device to fa ctory floor has been increasing. This project will contribute to the development of appropriate models as well as better numerical techniques for the process of chemical vapor deposition, one of the crucial production steps for computer chips. In this process, a thin layer of material is deposited to form either the electrical lines or the electronic devices that make up the computer chip in the final product.