Prototype and Distribution of Re-programmable Queuing Modules for Scalable Input Buffered Switches

用于可扩展输入缓冲交换机的可重新编程排队模块的原型和分发

• 批准号: 9818964
• 负责人: John Lockwood
• 金额: $ 77.35万
• 依托单位: University of Illinois at Urbana-Champaign
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1999
• 资助国家: 美国
• 起止时间: 1999-07-01 至 1999-10-29
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9818964&HistoricalAwards=false
• 关键词: Prototype; Distribution; Re; programmable; Queuing

The growing size of the Internet and the emergence of new applications that require Quality of Servicemandate radical changes in the way that network switches buffer data. This growing demand for bandwidth has pushed the architectures of existing output-buffered and shared-buffer switches to their maximum scalability limits. Input-buffered architectures overcome scalability limits by evenly distributing the queuing operations over all ports of the switch. Scaling the aggregate bandwidth of a switch, however, doesnot necessarily guarantee that an individual application's traffic flow is serviced fairly. Switches that provide per-flow queuing fairly allocate bandwidth and provide bounded delay. Existing switches provide either scalability or per-flow queuing, but none provide both.This research will implement a new hardware module that enables a scalable switch to provide per-flow queuing. This new module, called the WU-iiQ, will add enhanced queuing features to the highly scalable Washington University Gigabit Switch (WUGS). The logic for this card will be implemented with a Field Programmable Gate Array (FPGA) device, enabling it to implement a variety of queuing algorithms. The WU-iiQ will contain high-capacity Synchronous Dynamic Random Access Memory (SDRAM) to buffer ATM cells and Static Random Access Memory (SRAM) to store data structures and pointers for algorithms that perform per-flow queuing.The flexibility of the WU-iiQ has made the card of interest for several applications at this and other academic institutions. The reprogrammable logic on the WU-iiQ enables it to implement a variety of per-flow functions, including packet scheduling, traffic shaping, and congestion control. While all of these projects are different, they can all be implemented by using the same hardware.This project proposes to implement the WU-iiQ hardware and distribute it to research institutions that require such hardware to experiment with per-flow queuing mechanisms. Documentation for this WU-iiQ module will be made available via the World Wide Web. A library of commonly-needed hardware functions, including those that implement per-flow queuing operations, will be available for download.

Internet规模的不断扩大以及需要服务质量的新应用程序的出现，使得网络交换机缓冲数据的方式发生了根本性的变化。 这种对带宽不断增长的需求已经将现有的输出缓冲和共享缓冲交换机的架构推向了其最大的可扩展性极限。 输入缓冲架构通过将排队操作均匀分布在交换机的所有端口上来克服可扩展性限制。 然而，扩展交换机的总带宽并不一定保证公平地服务于单个应用程序的流量流。 提供按流排队的交换机公平地分配带宽并提供有限的延迟。 现有的交换机提供可扩展性或按流排队，但没有提供两者。本研究将实现一个新的硬件模块，使可扩展的交换机提供按流排队。 这个新模块称为WU-iiQ，将为高度可扩展的华盛顿大学千兆交换机（WUGS）添加增强的排队功能。 该卡的逻辑将采用现场可编程门阵列（FPGA）器件实现，使其能够实现各种排队算法。 WU-iiQ将包含高容量的同步动态随机存取存储器（SDRAM）来缓冲ATM信元和静态随机存取存储器（SRAM）来存储数据结构和用于执行每个流排队的算法的指针。 WU-iiQ上的可重编程逻辑使其能够实现各种逐流功能，包括分组调度、流量整形和拥塞控制。 虽然所有这些项目都是不同的，但它们都可以通过使用相同的硬件来实现。本项目建议实现WU-iiQ硬件，并将其分发给需要这种硬件的研究机构，以进行逐流排队机制的实验。 WU-iiQ模块的文档将通过万维网提供。 一个常用的硬件函数库，包括那些实现每个流排队操作的函数库，将可供下载。