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SBIR Phase I: Integration and Distribution of Low-Jitter On-Chip Clock for High-Speed Analog-to-Digital Converters

SBIR Phase I: Integration and Distribution of Low-Jitter On-Chip Clock for High-Speed Analog-to-Digital Converters
SBIR 第一阶段:高速模数转换器低抖动片上时钟的集成和分配
批准号:
9861554
负责人:
Deepnarayan Gupta
金额:
$10.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
1999
资助国家:
美国
项目状态:
已结题
起止时间:
1999-01-01 至 1999-06-30

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中文摘要
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英文摘要
9861554 This Small Business Innovation Research Phase I Project proposes to integrate two superconducting technologies--rapid-single-flux-quantum (RSFQ) and long-Josephson-junction (LJJ) - to build a fast digitizer instrument with on-chip clocking. HYPRES has demonstrated transient pulse capture at 16 GSamples/s with a flash analog-to-digital-converter (ADC) using an external clock. The ADC performance can be enhanced by replacing the external high-speed clock with an on-chip clock with very low timing jitter. The on-chip clock also simplifies the digitizer system by removing the requirement of external high-speed clock sources. A high-speed, frequency-tunable, single-flux-quantum (SFQ) clock with extremely narrow line width can be generated utilizing the resonant soliton modes of an underdamped long Josephson junction. In Phase I, a versatile multiple-frequency clock generator will be developed by combining the master long-junction clock with a new clock selector circuit and integrated with the wideband ADC. Two clock distribution schemes - through Josephson transmission lines (JTL) and ballistic transport on matched low-impedance micro-strip lines will be investigated. Successful integration of the long-junction on-chip clock with the flash ADC will lead to the demonstration of a simpler and lower cost transient digitizer instrument in Phase II. A transient digitizer instrument capable of sampling rates above 10 GSamples/s is not commercially available today, in spite of a growing demand in fields such as inertial confinement fusion and high-energy physics. HYPRES is developing such an instrument focusing on the $630M/year market for digitizer instruments. Elimination of expensive multi-GHz external clock generators will simplify the digitizer system and reduce its cost. A spin-off commercial application, employing the wideband ADC, is a communication signal processor, such as digital beam forming, targeted towards the satellite-communication hardware market of $500M/year.
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SBIR Phase I: Modified Doherty Transmit Architecture Employing Digital Signal Synthesis for Wideband RF Communication
  • 批准号:
    0944995
  • 项目类别:
    Standard Grant
  • 资助金额:
    $10.61万
  • 财政年份:
    2010
  • 负责人:
    Deepnarayan Gupta
  • 依托单位:
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  • 项目类别:
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  • 资助金额:
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  • 财政年份:
    2000
  • 负责人:
    Deepnarayan Gupta
  • 依托单位:
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