SBIR Phase I: Modified Doherty Transmit Architecture Employing Digital Signal Synthesis for Wideband RF Communication
SBIR Phase I: Modified Doherty Transmit Architecture Employing Digital Signal Synthesis for Wideband RF Communication
批准号:
0944995
负责人:
Deepnarayan Gupta
金额:
$10.61万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2010
资助国家:
美国
项目状态:
已结题
起止时间:
2010-01-01 至 2010-06-30
中文摘要
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英文摘要
This Small Business Innovation Research (SBIR) Phase I project proposes to demonstrate a Radio Frequency (RF) transmitter capable of groundbreaking performance for wireless infrastructure applications. Significant performance gains are expected from three main innovations in this highly-digital transmitter. First, building on the Doherty Power Amplifier (PA), a unique method of optimal digital synthesis of the RF drive signals is proposed; no analog upconversion, power-split and phase adjustment are needed. Digital signals drive a Doherty PA with modified bias, achieving higher efficiency than conventional designs. Second, efficiency and linearity are further improved over wide bandwidth (BW) by predistorting the digitized RF waveform directly. Third, a modular PA implementation is introduced, which is adaptively reconfigured to optimize the overall power efficiency with varying load. The design goals of the proposed work are: wide BW (100MHz), widely programmable carrier frequency (2.3-2.8GHz), high linearity (better than -65dBc), high output power (200W) and excellent average efficiency (60% at 10dB backoff). Analysis comparing the proposed PA to a conventional design shows average efficiency improvements of over 10% for maximum average power and up to 100% for 6dB backed off average power; the output power and average power gain are enhanced by 11% and 4× respectively. The broader impact/commercial potential of this project is considerable. Wireless network operators have long been demanding RF transmitters offering wider BW, better power efficiency, compact size and increased re-configurability to evolve their networks towards 4G at reasonable cost. Conventional transmitters cannot these requirements simultaneously. With groundbreaking performance, the proposed technology would be an ideal candidate for insertion into next generation 4G basestations. Commercialization of this work would result in significant savings in operational and capital expense for network operators, thereby enabling cost-effective 4G deployment with smaller, fewer and more aesthetic basestations. Reduction in energy consumption is also in line with the future roadmap of ?green technology?. Several options exist for product insertion into the wireless marketplace including: independent development of a complete basestation product, partnership with an established supplier of wireless basestations and licensing of inventions to external parties. The proposed research will increase understanding of PA nonlinearities, especially due to intrinsic device properties, and demonstrate the potential of a ?mixed signal? approach to realizing RF transmitters, wherein the rapidly advancing speed and complexity of digital circuits greatly improves the performance of traditionally analog RF systems.
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SBIR Phase II: Integration and Distribution of Low-Jitter On-Chip Clock for High-Speed Analog-to-Digital Converters
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批准号:9983361
-
项目类别:Standard Grant
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资助金额:$40.0万
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财政年份:2000
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负责人:Deepnarayan Gupta
-
依托单位:
SBIR Phase I: Integration and Distribution of Low-Jitter On-Chip Clock for High-Speed Analog-to-Digital Converters
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批准号:9861554
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项目类别:Standard Grant
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资助金额:$10.0万
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财政年份:1999
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负责人:Deepnarayan Gupta
-
依托单位:
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