Digital Protocol Hierarchy Analysis and Synthesis

系统级综合中的一个基本问题是难以将预先定义的协议作为约束来组合接口。这导致了一种混合级别的规范方法，很难创建，在一般性上有限，并且很难验证。在这项研究中，基于非确定的有限自动机，开发了一个通用数字系统设计的替代分层模型，以捕获系统协议和通信约束以及所需的控制和数据流活动。这种模型适用于使用BDD符号遍历技术的勘探。它们为满足复杂通信约束的系统数据流合成提供了一种机制。本项目所涉及的问题是：a)建立表示系统基本控制和数据流依赖的“因果自动机”的有效表示；b)建立支持大型复杂系统的分层抽象机制；c)用于综合时隐式状态遍历的剪枝技术；d)满足上述分析所规定的调度目标的分布式控制器综合。在该项目下开发的软件工具正通过互联网分发。

A fundamental problem in system level synthesis is the difficulty ofincorporating interfaces with pre-defined protocols as constraints. Thishas lead to a mixed level specification approach that is difficult tocreate, limited in generality and difficult to verify. In this research, aalternative hierarchical model for a generic digital system design is beingdeveloped based on a non-deterministic finite automata to capture systemprotocol and communication constraints as well as the required control anddata-flow activity. Such models are suitable for exploration using BDDsymbolic traversal techniques. They provide a mechanism for systematicdata-flow synthesis that meets complex communication constraints. Issuesaddressed in this project are: a) formulating an efficient representation fora "causal automata" which represents the essential control and data-flowdependencies for the system; b) formulating a mechanism for hierarchicalabstraction to support large, complex systems; c) pruning techniques onimplicit state traversal when used in synthesis; d) distributed controllersynthesis meeting scheduling goals imposed by the above analysis. Software tools developed under this project are being distributed via theInternet.