Production Language Based High-Level Synthesis

本研究的总体目标是创建一类新的合成工具，解决了复杂的路由器数据路径机器的设计下的约束条件下预定义的接口。 由于结果将与商业EDA设计工具集成，因此正在开发一种设计输出格式，该格式可以模拟并允许自动重新设计设计的选定部分。 在第二个任务中，近似顺序可达性分析被用来设计和实现优化和分区控制器设计的算法。 第三个任务是探索设计的控制和数据路径部分的调度算法。 最后，一个优化的编译器正在建立。 它包含解决高性能设计的编码问题的算法，并执行数据路径操作的重新调度，以最大限度地减少所需的资源，同时保持设计行为。

The overall goal of this research is to create a new class of synthesis tools which address the design of complex controller-data path machines under constraints of pre-defined interfaces. Because the results will be integrated with commercial EDA design tools, a design output format, which can be simulated and allows automated re-design of selected portions of the design, is being developed. In a second task, approximate sequential reachability analysis is being used to design and implement algorithms for optimizing and partitioning controller designs. The third task is to explore scheduling algorithms for both the control and data-path portions of the design. Finally, an optimizing compiler is being built. It contains algorithms which solve encoding issues for high performance designs, and performs re-scheduling of the data-path operations to minimize required resources while maintaining design behavior.