Transaction Level Modeling and Synthesis

摘要：在过去的二十年中，数字系统设计已经从大约10000门的大规模集成电路发展到目前10-20M门的设计。在此期间，基本的设计抽象已经从基于图形到基于语言，使用rt级规范。尽管进行了多次尝试，高层表示并没有为系统级设计抽象提供实用的机制。在这项工作中，我们绕过了传统的行为方法，并在事务体系结构级别创建了一个新的综合抽象。从根本上说，事务限制了顺序和功能行为，但允许替代结构和通信自由。使用为形式化验证开发的技术作为基础，提出的框架承诺将架构级建模与顺序约束的rt级设计联系起来。因此，在系统级别需要详细的顺序建模的困难权衡可以在优化框架中表示。该项目将构建原型工具，产生适合于传统合成的rt级输出，作为技术的驱动和评估。

Abstract:Over the last twenty years digital system design has gone from LSI circuits of about 10,000 gates to current designs with 10-20M gates. During this time the basic design abstraction has gone from graph based to language based using RT-level specifications. Despite numerous attempts, high level representations have not provided a practical mechanism for system level design abstraction. In this work, we are side stepping conventional behavioral approaches and are creating a new synthesis abstraction at the transaction architectural level. Fundamentally, transactions have constrained sequential and functional behavior but allow alternative construction and communication freedom. Using techniques developed for formal verification as a basis, the proposed framework promises to link architectural level modeling with sequentially constrained RT-level design. Thus, difficult trade-offs at the system level which require detailed sequential modeling can be represented within an optimization framework. The project will construct prototype tools producing RT-level output suitable for conventional synthesis as both driver and evaluation of the techniques.