CAREER: Incorporating Technology Scaling into the Design, Evaluation, and Implementation of Computer Architectures

职业:将技术扩展纳入计算机架构的设计、评估和实现中

基本信息

  • 批准号:
    9984336
  • 负责人:
  • 金额:
    $ 20.1万
  • 依托单位:
  • 依托单位国家:
    美国
  • 项目类别:
    Standard Grant
  • 财政年份:
    2000
  • 资助国家:
    美国
  • 起止时间:
    2000-09-01 至 2005-08-31
  • 项目状态:
    已结题

项目摘要

ABSTRACTPROPOSAL NUMBER: 9984336TITLE: Incorporating Technology Scaling into the Design, Evaluation, and Implementation of Computer ArchitecturesPI: Stephen W. Keckler, University of Texas at Austin The objectives for the research funded by this CAREER proposal are to investigate computer architectures that simultaneously address the challenges of deep-submicron technologies and meet the needs of modern dynamic applications. The most significant technology challenges are the diverging speeds of transistors and wires, increased power consumption and heat generation in integrated circuits, and higher susceptibility to transient logic faults due to decreasing feature sizes.This research includes three components. First, accurate technology models for future silicon fabrication technologies are developed. The focus is on communication delay, both along wires and within microarchitecture structures such as register files and ALUs and on the reliability of microprocessor components when subjected to external energy sources. Second, these models are incorporated into the SimpleScalar toolset to evaluate existing architectures under these new technological constraints and provide a platform for evaluating future architectures. Third, multiple processor cores on a chip are investigated as a means to construct a "server-on-a-chip" and to build a system that tolerates transient faults. The necessary features of this multicore architecture are hardware and system software that dynamically schedule jobs to meet latency, throughput, and redundancy (for reliability) requirements of the workloads.
摘要提案编号:9984336标题:计算机体系结构的设计、评估和实现中的扩展技术。德克萨斯大学奥斯汀分校 由该CAREER提案资助的研究目标是调查同时解决深亚微米技术挑战并满足现代动态应用需求的计算机体系结构。 最重要的技术挑战是晶体管和导线的发散速度,增加的功耗和集成电路中的发热,以及由于特征尺寸减小而对瞬态逻辑故障的更高敏感性。首先,为未来的硅制造技术开发精确的技术模型。重点是通信延迟,无论是沿着线和微架构结构,如寄存器文件和ALU和可靠性的微处理器组件时,受到外部能源。 其次,这些模型被纳入SimpleScalar工具集,以评估这些新技术约束下的现有架构,并为评估未来的架构提供一个平台。 第三,在一个芯片上的多个处理器核心的调查作为一种手段来构建一个“服务器上的一个芯片”,并建立一个系统,容忍瞬态故障。 这种多核架构的必要功能是动态调度作业以满足工作负载的延迟、吞吐量和冗余(用于可靠性)要求的硬件和系统软件。

项目成果

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Stephen Keckler其他文献

Stephen Keckler的其他文献

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{{ truncateString('Stephen Keckler', 18)}}的其他基金

SHF:Small: Locality-Driven Architectures for Scalable Multicore Systems
SHF:Small:用于可扩展多核系统的局部驱动架构
  • 批准号:
    0916745
  • 财政年份:
    2009
  • 资助金额:
    $ 20.1万
  • 项目类别:
    Standard Grant
EAGER: An Energy-Driven Point Design Study for Exascale Computing
EAGER:针对百亿亿次计算的能量驱动点设计研究
  • 批准号:
    0936700
  • 财政年份:
    2009
  • 资助金额:
    $ 20.1万
  • 项目类别:
    Standard Grant
CPA-CSA: On-Chip Interconnection Networks for Scalable Integrated Systems
CPA-CSA:用于可扩展集成系统的片上互连网络
  • 批准号:
    0811056
  • 财政年份:
    2008
  • 资助金额:
    $ 20.1万
  • 项目类别:
    Standard Grant
Support for the 41st International Symposium on Microarchitecture
支持第41届国际微架构研讨会
  • 批准号:
    0849060
  • 财政年份:
    2008
  • 资助金额:
    $ 20.1万
  • 项目类别:
    Standard Grant

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