CPA-CSA: On-Chip Interconnection Networks for Scalable Integrated Systems

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The successive innovations in semiconductor manufacturing over thelast 35 years of Moore's law have turned what used to be a room-sizedcomputer system into a single chip composed of billions oftransistors. These levels of integration have forced a change towardparallelism in computer system design, including both single-chipmultiprocessors and systems-on-a-chip. Today, these chips have a fewtens of individual processors but future scaling will make hundreds orthousands available on a chip. Critical to the success of such systemsis the hardware network that enables the processors on the chip tocommunicate with one another. Today's chips typically employ simplenetworks-on-chip (NOCs) such as bus, ring, or small grid. Futuresystems with numerous processors will need scalable and innovativeNOCs to provide high communication bandwidth, low latency, and lowpower consumption.This project seeks to develop scalable NOCs that are well suited toswitch and wire capabilities in emerging chip fabricationtechnologies. In particular, the project would investigate new NOCtopologies that exploit the enormous number of on-chip wires while reducing the number of hops to travel from a source to a destination. Asecond challenge is avoiding congestion in the network, much likeavoiding automobile traffic congestion at rush hour. The investigationwill develop new methods of monitoring the status of the routers andlinks in the network so that network messages can route themselvesaround network hotspots, improving network latency and bandwidth forall traffic. An important outcome of this research would be a publicrepository of network traces for different types of on-chip network traffic that will help improve the experimental methods of all NOC researchers.