CPA-CSA: On-Chip Interconnection Networks for Scalable Integrated Systems

CPA-CSA：用于可扩展集成系统的片上互连网络

• 批准号: 0811056
• 负责人: Stephen Keckler
• 金额: $ 27.49万
• 依托单位: University of Texas at Austin
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-08-01 至 2012-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0811056&HistoricalAwards=false
• 关键词: CPA; CSA; Chip; Interconnection; Networks

The successive innovations in semiconductor manufacturing over thelast 35 years of Moore's law have turned what used to be a room-sizedcomputer system into a single chip composed of billions oftransistors. These levels of integration have forced a change towardparallelism in computer system design, including both single-chipmultiprocessors and systems-on-a-chip. Today, these chips have a fewtens of individual processors but future scaling will make hundreds orthousands available on a chip. Critical to the success of such systemsis the hardware network that enables the processors on the chip tocommunicate with one another. Today's chips typically employ simplenetworks-on-chip (NOCs) such as bus, ring, or small grid. Futuresystems with numerous processors will need scalable and innovativeNOCs to provide high communication bandwidth, low latency, and lowpower consumption.This project seeks to develop scalable NOCs that are well suited toswitch and wire capabilities in emerging chip fabricationtechnologies. In particular, the project would investigate new NOCtopologies that exploit the enormous number of on-chip wires while reducing the number of hops to travel from a source to a destination. Asecond challenge is avoiding congestion in the network, much likeavoiding automobile traffic congestion at rush hour. The investigationwill develop new methods of monitoring the status of the routers andlinks in the network so that network messages can route themselvesaround network hotspots, improving network latency and bandwidth forall traffic. An important outcome of this research would be a publicrepository of network traces for different types of on-chip network traffic that will help improve the experimental methods of all NOC researchers.

在摩尔定律存在的过去35年里，半导体制造业的不断创新，已经把一个房间大小的计算机系统变成了一个由数十亿个晶体管组成的单一芯片。这些级别的集成迫使计算机系统设计转向并行，包括单芯片多处理器和单片系统。今天，这些芯片只有几十个单独的处理器，但未来的扩展将使一个芯片上有成百上千个处理器。这种系统成功的关键是硬件网络，它使芯片上的处理器能够相互通信。今天的芯片通常采用简单的片上网络（noc），如总线、环或小网格。未来具有众多处理器的系统将需要可扩展和创新的ocs来提供高通信带宽、低延迟和低功耗。该项目旨在开发可扩展的noc，这些noc非常适合新兴芯片制造技术中的开关和线路功能。特别是，该项目将研究新的notopologies，利用大量的片上导线，同时减少从源到目的地的跳数。第二个挑战是避免网络拥堵，就像避免高峰时段的汽车交通拥堵一样。该研究将开发监测网络中路由器和链路状态的新方法，以便网络消息可以在网络热点周围路由，改善所有流量的网络延迟和带宽。这项研究的一个重要成果将是建立一个针对不同类型片上网络流量的网络轨迹的公共存储库，这将有助于改进所有NOC研究人员的实验方法。