SHF:Small: Locality-Driven Architectures for Scalable Multicore Systems

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The successive innovations in semiconductor manufacturing over the last 35 years of Moore's law have turned what used to be a room-sized computer system into a single chip composed of billions of transistors. These levels of integration have forced a change toward parallelism in computer system design, including both single-chip multiprocessors and systems-on-a-chip. Today, these chips have a few tens of individual processors but future scaling will make possible hundreds or thousands of them on a chip. Two important challenges have emerged which threaten to hinder performance scaling in multicore systems. First, while technology scaling will continue to enable increased transistor counts for the foreseeable future, power and thermal limitations will prevent all but a small fraction of them to be operating simultaneously at full speed. Second, the speed of the communication paths from the multicore chip to its external memory and to other processors is increasing at a slow rate. Because these communication paths must be shared by more and more on-chip processing cores, the paths must be used as efficiently as possible to prevent them from becoming a bottleneck in the system.This project seeks to develop new computer hardware and software mechanisms that exploit data locality in high performance systems, including repeated use of a data item as well as use of multiple data items that lie near one another in memory. In particular, the project will develop hardware mechanisms for bulk data transfers that support renaming, packing, and integration into the virtual memory system. The PI will also develop hardware mechanisms in the on-chip memory system that will allow it to adapt to different programming primitives as well as to different coherence needs among the processing cores. The mechanisms will be evaluated in terms of effectiveness and programmability using a range of applications.This research aims to develop technologies critical to emerging parallel multicore chips, without which such chips will not be able to meet performance and power goals. Enabling enhanced performance in a power-efficient manner is critical to all deployments of future computing platforms, including those for science, commerce, and national security. The broader impact of this research will include training graduate and undergraduate students as researchers, while also working to increase participation of underrepresented groups in computing. The primary outreach activity will include participation in a summer camp to attract high-school girls to computer science.