NeuroSoC_A multiprocessor system on chip with in-memory neural processing unit

在边缘部署智能带来了许多挑战，因为设备需要低成本，因此，它们通常受到计算能力、内存和能源资源的限制。这些限制与更高级的人工智能算法的需求不兼容，需要兆字节的存储空间和每次推理的数十个GOPS，需要更精简的边缘人工智能算法。目前（少数）边缘人工智能芯片依赖于90或40nm的低成本工艺技术，在某些情况下高达16nm，功率效率在1-5 TOPS/w之间，功率密度高达1 TOPS/mm2。最近，一些工业项目和一些产品已经开始追求神经形态和内存计算，但这些努力都没有达到与大规模生产和成本兼容的成熟水平，而且，它们所依赖的技术基础要么不能扩展到更先进的节点（闪存），要么针对人工智能计算算法，其实际应用尚未得到充分证明（例如，尖峰）。相反，NeuroSoC的方法是依靠坚实、成熟、合格、可靠的相变存储器技术来创建一条经过工业验证的路径，以超越最先进的技术，因此，NeuroSoC芯片的预产品演示技术将是全球首例。NeuroSoC的目标是在FD-SOI 28nm CMOS技术中开发一种先进的多处理器片上系统原型，该原型基于现有RISC-V微处理器实现的增强版本，紧密集成了AIMC IMNPU单元、本地数字处理子系统和功能安全的多处理器主机子系统，同时全面覆盖IMNPU安全方面，以满足广泛的边缘人工智能应用需求。该项目将利用意法半导体独特的高密度嵌入式PCM电池工艺技术，该技术密度更大，而且在工业领域中只有这种技术适合嵌入式应用

Deployment of intelligence at the edge presents many challenges because devices need to be low-cost and, as such, they are often constrained in computing capacity, memory, and energy resources. These constraints are not compatible with the need for much more advanced AI algorithms calling for Mbytes of storage and tens of GOPS per inference and call for leaner edge AI algorithms. The current state of the art for (the few) edge-AI chips relies on low-cost process technologies at 90 or 40nm and in some cases up to 16nm, with power efficiency between 1-5 TOPS/w and power densities up to 1 TOPS/mm2. Recently several industrial projects and a few products have started to surface pursing neuromorphic and in memory computing, but none of these efforts have reached a level of maturity compatible with a mass volume production and cost, and, moreover the technology base they rely on is either not scalable to more advanced nodes (flash) or, targeting AI computing algorithms whose practical applications are yet to be fully proven (e.g., spiking). The NeuroSoC approach instead is to rely on a solid, mature, and qualified reliable Phase Change Memory technology to create an industrially proven path to go past the state of the art, as such, the NeuroSoC chip pre-product demonstration of the technology will be the first of his kind worldwide. NeuroSoC’s aim is to develop an advanced Multi-Processor System on Chip prototype in FD-SOI 28nm CMOS technology that tightly integrates an AIMC IMNPU unit, a local digital processing subsystem, and functional safe multiprocessor host subsystems based on an enhanced version of existing RISC-V microprocessor implementation, while covering IMNPU security aspects holistically to tackle the requirements of a wide set of edge-AI applications. The project will leverage STMicroelectronics’s unique highdensity embedded PCM cell process technology being the denser and only such technology qualified and mature for embedded use in the industry world