ITR: Application-Specific Reconfigurable Microarchitectural Enhancements for Embedded Processors in High-Performance Hardware/Software Codesigns

该项目探讨了嵌入式处理器内核的特定应用定制是否可以保留处理器架构的基本优势，同时减轻相关的缺陷，例如性能降低和功耗过高。所采取的基本方法是在编译时识别应用程序的属性，并在嵌入式处理器执行程序时对其进行动态开发。这些属性的基本特征是，它们的存在可以被编译器静态地识别，并且当动态地利用它们时，它们会导致性能的显著提高。通过嵌入性能提升知识，而不是通过狭窄的伊萨通道进行通信，可以扩展到微架构。可以用这种应用程序专用信息增强的微体系结构特征包括分支预测器、该高速缓存子系统和动态调度硬件。虽然所提出的方法的目的是在处理器定制的基础上，特定于应用程序的知识，它这样做，而不违反处理器架构提供的灵活性。通过微架构的可重新配置性进行后期定制，可以利用应用程序和架构特性，从而提高性能，降低功耗和面积，同时保持通用架构的体积和灵活性优势。

The project explores the possibility of whether application-specific customizations of embedded processor cores can preserve the fundamental benefits of a processor architecture, while alleviating the associated deficiencies, such as reduced performance and excessive power consumption. The fundamental approach undertaken is the identification of application properties during compile time and their dynamic exploitation during program execution by the embedded processor. The basic characteristic of these properties is that their existence can be statically identifiable by the compiler, and that they lead to significant improvements in performance when exploited dynamically. Extended transfer to the microarchitecture is to occur by embedding performance-boosting knowledge, rather than communicating it through narrow ISA channels. Microarchitectural features that can be enhanced with such application-specific information include the branch predictor, the cache subsystem and the dynamic scheduling hardware. While the proposed approach aims at processor customization based on application-specific knowledge, it does so without violating the flexibility offered by processor architectures. Late customization through microarchitectural reconfigurability exploits application and architecture characteristics, thus boosting performance, reducing power and area, while keeping intact the volume and flexibility benefits of general purpose architectures.