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ITR: Application-Specific Reconfigurable Microarchitectural Enhancements for Embedded Processors in High-Performance Hardware/Software Codesigns

ITR：高性能硬件/软件协同设计中嵌入式处理器的特定于应用的可重构微架构增强

基本信息

批准号：
0082325
负责人：
Alex Orailoglu
金额：
$ 39.04万
依托单位：
University of California-San Diego
依托单位国家：
美国
项目类别：
Continuing Grant
财政年份：
2000
资助国家：
美国
起止时间：
2000-09-01 至 2006-08-31
项目状态：
已结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=0082325&HistoricalAwards=false
关键词：
ITR Application Specific Reconfigurable Microarchitectural

项目摘要

The project explores the possibility of whether application-specific customizations of embedded processor cores can preserve the fundamental benefits of a processor architecture, while alleviating the associated deficiencies, such as reduced performance and excessive power consumption. The fundamental approach undertaken is the identification of application properties during compile time and their dynamic exploitation during program execution by the embedded processor. The basic characteristic of these properties is that their existence can be statically identifiable by the compiler, and that they lead to significant improvements in performance when exploited dynamically. Extended transfer to the microarchitecture is to occur by embedding performance-boosting knowledge, rather than communicating it through narrow ISA channels. Microarchitectural features that can be enhanced with such application-specific information include the branch predictor, the cache subsystem and the dynamic scheduling hardware. While the proposed approach aims at processor customization based on application-specific knowledge, it does so without violating the flexibility offered by processor architectures. Late customization through microarchitectural reconfigurability exploits application and architecture characteristics, thus boosting performance, reducing power and area, while keeping intact the volume and flexibility benefits of general purpose architectures.

该项目探讨了嵌入式处理器内核的特定于应用的定制是否可以保留处理器架构的基本优势，同时减轻相关缺陷（例如性能下降和功耗过高）的可能性。所采用的基本方法是在编译时识别应用程序属性，并在嵌入式处理器执行程序期间动态利用它们。这些属性的基本特征是编译器可以静态识别它们的存在，并且动态利用它们可以显着提高性能。向微体系结构的扩展转移是通过嵌入性能提升知识来实现的，而不是通过狭窄的 ISA 通道进行通信。可以使用此类特定于应用程序的信息增强的微架构功能包括分支预测器、缓存子系统和动态调度硬件。虽然所提出的方法旨在基于特定于应用程序的知识进行处理器定制，但它不会违反处理器架构提供的灵活性。通过微架构可重构性的后期定制可利用应用程序和架构特性，从而提高性能、降低功耗和面积，同时保持通用架构的体积和灵活性优势。