ITR: Application-Specific Reconfigurable Microarchitectural Enhancements for Embedded Processors in High-Performance Hardware/Software Codesigns

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The project explores the possibility of whether application-specific customizations of embedded processor cores can preserve the fundamental benefits of a processor architecture, while alleviating the associated deficiencies, such as reduced performance and excessive power consumption. The fundamental approach undertaken is the identification of application properties during compile time and their dynamic exploitation during program execution by the embedded processor. The basic characteristic of these properties is that their existence can be statically identifiable by the compiler, and that they lead to significant improvements in performance when exploited dynamically. Extended transfer to the microarchitecture is to occur by embedding performance-boosting knowledge, rather than communicating it through narrow ISA channels. Microarchitectural features that can be enhanced with such application-specific information include the branch predictor, the cache subsystem and the dynamic scheduling hardware. While the proposed approach aims at processor customization based on application-specific knowledge, it does so without violating the flexibility offered by processor architectures. Late customization through microarchitectural reconfigurability exploits application and architecture characteristics, thus boosting performance, reducing power and area, while keeping intact the volume and flexibility benefits of general purpose architectures.