CISE Research Infrastructure: An Infrastructure for Integrated Systems Education and Innovation

0101254斯科特·A·霍克华盛顿大学研究基础设施：集成系统教育和创新的基础设施本提案中包含的研究代表了对单芯片系统未来的广泛调查。我们将寻求开发一种设计方法，能够为众多设计领域提供多种不同资源类型的好处。为了支持这种尖端硅系统的设计，我们将开发创新技术来处理大量设计问题。这些将包括对芯片设计中的以下关键问题的研究：开发将射频和模拟组件集成到未来1V SoC设计中的技术。创建高性能、高能效的数字逻辑系列，以支持这些系统的严格要求。研究SoC设计的可重构子系统，提供支持多协议和多算法系统的制造后定制。针对复杂、异质系统的集成测试方法，可提供完整的系统测试。完整的模拟和设计方法，可处理完整的系统集成、架构探索和验证。除了开发未来芯片设计的新方法外，我们还将开发培养未来芯片设计人员的创新技术。通过提供VLSI/CAD、嵌入式系统和复杂系统设计的综合课程，我们将帮助培养能够利用这些全新的设计技术和机会的系统架构师。我们还将寻求增加新选民在芯片设计方面的机会，特别是代表不足的群体，以帮助增加新设计师的渠道。

0101254Scott A. HaukUniversity of WashingtonCISE Research Infrastructure: An Infrastructure for Integrated Systems Education and Innovation The research contained in this proposal represents a wide-ranging investigation into the future of single-chip systems. We will seek to develop a design methodology that can provide the benefits of multiple different resource types for numerous design domains. To support the design of such cutting-edge silicon systems, we will develop innovative techniques to handle numerous design issues. These will include investigations into the following critical issues in chip design: Development of techniques for integrating RF and Analog components into future 1V SoC designs. Creation of high-performance, power efficient digital logic families for supporting the stringent requirements of these systems. Investigation into reconfigurable subsystems for SoC designs, providing post-fabrication customization for support of multi-protocol and multi-algorithm systems. Integrated testing methodologies for complex, heterogeneous systems that can provide complete system test. Complete simulation and design methodologies that can handle complete system integration, architectural exploration, and validation. In addition to the development of new approaches to future chip design, we will also develop innovative techniques for educating future chip designers. By providing an integrated curriculum in VLSI/CAD, embedded systems, and complex system design, we will help create system architects capable of harnessing these radically new design techniques and opportunities. We will also seek to increase the opportunities in chip design for new constituents, especially under-represented groups to help increase the pipeline of new designers