Achieving High-Performance Reconfigurable Computing in Commodity Devices

在商品设备中实现高性能可重构计算

• 批准号: 0426147
• 负责人: Scott Hauck
• 金额: $ 32.5万
• 依托单位: University of Washington
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2004
• 资助国家: 美国
• 起止时间: 2004-11-01 至 2008-10-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0426147&HistoricalAwards=false
• 关键词: Achieving; Performance; Reconfigurable; Computing; Commodity

Achieving High-Performance Reconfigurable Computing in Commodity DevicesAbstractFPGAs are chips that can be programmed and reprogrammed to implement complex digital logic. They combine the performance of hardware with the flexibility of software. Potential applications range from hardware accelerators for high-performance computers, as well as in everyday electronic devices. Thus, improving their performance is of significant interest.Although FPGAs can provide high performance for a wide range of applications, their achieved clock cycles are typically 5x-10x slower than other circuits. This is due to the programmable nature of the underlying hardware, as well as the limitations in the input circuits.FPGAs can support much higher theoretical clock rates than currently can be achieved in practice. This research will develop architectural features and tools needed to realize this potential. This approach will combine established techniques with new algorithms for generating and mapping highly pipelined circuits. The key is to allow for very significant levels of circuit pipelining in situations that demand it, while trading area for performance.We will also optimize the FPGA architectures to support pipelining, while not adversely affecting general-purpose designs. This will include optimized logic blocks that can support aggressive pipelining, as well as routing designed for interconnect pipelining.This proposal contains new approaches to radically increase the speed of FPGAs, a major building block in today's electronics systems. By providing faster hardware, we can provide greater flexibility, capabilities, and speed in many different systems. This may include high-end computers with reconfigurable hardware units, and versatile electronics like multi-network, multi-service cell phones and enhanced multi-media capable PDAs.

在商品设备中实现高性能可重构计算摘要FPGA是可以编程和重新编程以实现复杂数字逻辑的芯片。 它们联合收割机了硬件的性能和软件的灵活性。潜在的应用范围从高性能计算机的硬件加速器到日常电子设备。 虽然FPGA可以为广泛的应用提供高性能，但其实现的时钟周期通常比其他电路慢5倍至10倍。 这是由于底层硬件的可编程特性以及输入电路的局限性。FPGA可以支持比目前实际上高得多的理论时钟速率。 这项研究将开发实现这一潜力所需的架构功能和工具。 这种方法将联合收割机建立的技术与新的算法相结合，用于产生和映射高度流水线化的电路。 关键是在需要的情况下允许非常显著的电路流水线水平，同时以面积换取性能。我们还将优化FPGA架构以支持流水线，同时不会对通用设计产生不利影响。 这将包括优化的逻辑块，可以支持积极的流水线，以及路由设计的互连流水线。这一建议包含新的方法，从根本上提高FPGA的速度，在今天的电子系统的主要组成部分。 通过提供更快的硬件，我们可以在许多不同的系统中提供更大的灵活性、功能和速度。 这可能包括具有可重新配置硬件单元的高端计算机，以及多功能电子设备，如多网络、多服务蜂窝电话和增强型多媒体PDA。