SHF: Small: CGRAs - Control and Architecture for Next-Generation FPGAs

SHF：小型：CGRA - 下一代 FPGA 的控制和架构

• 批准号: 1116248
• 负责人: Scott Hauck
• 金额: $ 45万
• 依托单位: University of Washington
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-09-01 至 2015-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1116248&HistoricalAwards=false
• 关键词: SHF; Small; CGRAs; Control; Architecture

This research effort is developing new electronic devices and mapping software to improve the speed, power-efficiency, and cost of digital electronics. They start with the concept of the Field-Programmable Gate Array (FPGA), logic chips that can be programmed and reprogrammed to implement complex digital circuits. FPGAs are an important driver for the semiconductor industry, reaching almost $3B in annual worldwide sales. Current FPGAs are essentially seas of 1-bit compute units, each configured to do one function over and over. To support more complex operations modern devices have a sprinkling of more complex units, including multipliers and memories, which have a more multi-bit flavor. All the components of these devices are interconnected via a static, single-bit routing network, and are primarily programmed in hardware description languages such as Verilog or VHDL. An FPGA single-bit programmability provides a great deal of flexibility for creating arbitrary logic, but has significant inefficiencies as well.Word-based architectures, that compute and route multi-bit values simultaneously, can be much more efficient than standard FPGAs. Word-based alternatives to FPGAs exist, such as CGRAs and MPPAs, but limitations in their control systems significantly reduce their quality and usefulness for many applications.One of the major thrusts of this work is to merge together the customizable logic of FPGAs with the time-multiplexing ability of MPPAs and CGRAs, as well as the complex control flow supported by modern multi-core CPUs. Unlike a standard FPGA, that statically configures all of its resources to do a single task, this system allows each compute element in the device to run a small program. This provides a significantly greater compute density in these devices. However, to boost this even further, they are exploring mechanisms to make use of branching and conditional operation. Specifically, where a microprocessor might take a branch based upon a loop condition or as part of an if-then-else construct, their hardware system can either change the instructions loaded during that cycle, or branch to a different portion of the overall operation. However, unlike MPPAs and CGRAs, their system can perform data-dependent instruction selection within a large, automatically mapped computation region operating in lock-step. Alternatively, for control-heavy portions of a computation they can embed complete, simple VLIW processors into the fabric of their system.To support these efforts, they are developing new compilation strategies to convert computations into efficient implementations on these architectures. They are also looking at the hardware resources required to support these operations. This includes methods for stalling portions of the array when their communication demands temporarily cannot be met, as well as mechanisms to synchronize the program counters of regions of the array operating in lock-step.When combined, they estimate these systems will provide an order of magnitude improvement in area-power product, and at least a factor of 2 performance improvement, over FPGAs. The resulting hardware and software systems should be able to significantly reduce the power consumption, lower the cost, and increase the speed of a large swath of electronic systems. Also, their improved programming models will make these systems easier to develop and maintain.This effort also includes a focus on improving the diversity of the engineering workforce at both the graduate and undergraduate level, with mentoring and research opportunities at each level. All of these activities are done within an overall effort towards outreach to underrepresented groups.

这项研究工作正在开发新的电子设备和绘图软件，以提高数字电子产品的速度、功率效率和成本。他们从现场可编程门阵列（FPGA）的概念开始，可以编程和重新编程以实现复杂数字电路的逻辑芯片。fpga是半导体行业的重要推动力，全球年销售额接近30亿美元。当前的fpga本质上是一堆1位计算单元，每个计算单元被配置为反复执行一个功能。为了支持更复杂的操作，现代设备有一些更复杂的单元，包括乘数器和存储器，它们具有更多的多比特风格。这些设备的所有组件都通过静态的单比特路由网络相互连接，并且主要用硬件描述语言（如Verilog或VHDL）进行编程。FPGA的单比特可编程性为创建任意逻辑提供了很大的灵活性，但也有显著的低效率。同时计算和路由多比特值的基于字的架构比标准fpga要高效得多。现有基于字的fpga替代品，如CGRAs和mppa，但其控制系统的局限性大大降低了其质量和在许多应用中的实用性。这项工作的主要重点之一是将fpga的可定制逻辑与mppa和CGRAs的时间复用能力以及现代多核cpu支持的复杂控制流合并在一起。与标准FPGA静态配置其所有资源以执行单个任务不同，该系统允许设备中的每个计算元素运行一个小程序。这在这些设备中提供了更大的计算密度。然而，为了进一步提高这一点，他们正在探索利用分支和条件操作的机制。具体来说，微处理器可能会根据循环条件或作为if-then-else构造的一部分进行分支，它们的硬件系统可以改变在该周期中加载的指令，或者分支到整个操作的不同部分。然而，与mppa和CGRAs不同的是，它们的系统可以在一个大的、自动映射的计算区域内以锁步操作执行依赖数据的指令选择。或者，对于计算中需要大量控制的部分，他们可以将完整、简单的VLIW处理器嵌入到系统结构中。为了支持这些努力，他们正在开发新的编译策略，将计算转换为这些体系结构上的有效实现。他们还在研究支持这些操作所需的硬件资源。这包括在通信需求暂时无法满足时使部分数组停止的方法，以及同步以锁步操作的数组区域的程序计数器的机制。当组合在一起时，他们估计这些系统将在面积功率产品上提供一个数量级的改进，并且至少比fpga提高2倍的性能。由此产生的硬件和软件系统应该能够显著降低功耗，降低成本，并提高大量电子系统的速度。此外，他们改进的编程模型将使这些系统更容易开发和维护。这项工作还包括在研究生和本科生水平上提高工程劳动力的多样性，并在每个水平上提供指导和研究机会。所有这些活动都是在向代表人数不足的群体伸出援手的总体努力范围内进行的。