Trace-Driven Evaluations of the Memory Behavior of Large Commercial Applications

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Computer architecture research is based on experimental evaluation of application behavior.One critical issue in the architecture of high-end enterprise servers is the design of the memoryhierarchy, which must be designed to support current and future data-intensive applications.Few evaluations of the memory behavior of large commercial applications exist, especially in thepublic domain. The research proposed here is based on a collaboration between IBM and USC totake advantage of the IBM Watson Server Performance Laboratory to explore the memorybehavior of high-end commercial applications.More specifically, it is proposed to use the IBM MemorIES board to collect bus activitytraces from a modern server machine running large, finely tuned OLTP, DSS and Web workloads.Because of the sheer size of the traces, samples of transaction records will be collected only in selected time intervals.Besides obtaining traces, the goal of this project is to characterize the memorybehavior of these applications, to evaluate alternative memory hierarchies for futurehigh-end commercial servers, and to explore new multiprocessor architectures forcommercial systems. The experimental environment provided by the IBM Watson Server Performance Laboratorycost millions of dollars and years of effort to setup. This proposed research will leverage theseefforts. It is a unique opportunity to collect and disseminate traces and experimental datawhich would be practically impossible to obtain under any reasonable research budget.