ITR/SY: SCMP -- A Single-Chip Parallel Computer

ITR/SY：SCMP——单芯片并行计算机

• 批准号: 0113948
• 负责人: James Baker
• 金额: $ 32.8万
• 依托单位: Virginia Polytechnic Institute and State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2001
• 资助国家: 美国
• 起止时间: 2001-09-01 至 2004-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0113948&HistoricalAwards=false
• 关键词: ITR; SY; SCMP; Single; Chip

This project will investigate the architecture and design of a single-chipparallel computer system. As technology continues to improve and transistorsizes decrease, the latency of on-chip interconnect wires will have agreater impact on the performance of computer systems. In the future,computer designers will need to develop architectures that avoid the use oflong interconnect wires in order to reduce the effect of this latency. Onesuch approach would be to include a number of small, simple processorstogether on a single chip, forming a single-chip parallel computer. Thiswould reduce the effect of the latency because the length of theinterconnect wires would depend on the size and complexity of theindividual processors, not the size of the entire system. By keeping theprocessors simple, long interconnect wires will not be necessary. Thechallenge to designing such a system is determining the features that thearchitecture must include. This research project will investigatearchitectural features that provide low-overhead support for parallelprograms, applying them to the design of the SCMP (Single-ChipMessage-Passing) parallel computer. Through the extensive use ofsimulation, the design and performance of the SCMP system will be analyzedand compared to other computer architectures.

本计画将探讨单晶片平行电脑系统之架构与设计。随着技术的不断进步和晶体管尺寸的不断减小，片上互连线的延迟将对计算机系统的性能产生更大的影响。在未来，计算机设计者将需要开发避免使用长互连线的架构，以减少这种延迟的影响。一种方法是在一个芯片上集成许多小而简单的处理器，形成一个单芯片并行计算机。这将减少延迟的影响，因为互连线的长度将取决于单个处理器的大小和复杂性，而不是整个系统的大小。通过保持处理器简单，长互连线将是不必要的。设计这样一个系统的挑战是确定架构必须包括的特性。本研究计画将探讨能提供低开销平行程式支援的架构特性，并将其应用于SCMP（单芯片讯息传递）平行电脑的设计。通过大量使用仿真，SCMP系统的设计和性能将被分析，并与其他计算机体系结构进行比较。