ITR/SY: SCMP -- A Single-Chip Parallel Computer

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This project will investigate the architecture and design of a single-chipparallel computer system. As technology continues to improve and transistorsizes decrease, the latency of on-chip interconnect wires will have agreater impact on the performance of computer systems. In the future,computer designers will need to develop architectures that avoid the use oflong interconnect wires in order to reduce the effect of this latency. Onesuch approach would be to include a number of small, simple processorstogether on a single chip, forming a single-chip parallel computer. Thiswould reduce the effect of the latency because the length of theinterconnect wires would depend on the size and complexity of theindividual processors, not the size of the entire system. By keeping theprocessors simple, long interconnect wires will not be necessary. Thechallenge to designing such a system is determining the features that thearchitecture must include. This research project will investigatearchitectural features that provide low-overhead support for parallelprograms, applying them to the design of the SCMP (Single-ChipMessage-Passing) parallel computer. Through the extensive use ofsimulation, the design and performance of the SCMP system will be analyzedand compared to other computer architectures.