Modeling of Unified Channel Mobility for Quantum Hydrodynamic Simulation of Nanoscale MOSFETs

目前，cmos技术正从180 nm节点向130 nm节点迈进。对于100 nm-130 nm的产生技术，必须重新审视晶体管设计的许多关键问题。其中之一是发生在非尺度MOS器件中的非平衡输运。由于器件的不断缩小，栅极长度现在变得与非弹性平均自由程相当或更小。在这种情况下，MOS器件中载流子的非平衡/非局域输运需要与传统方法有很大不同的描述。在本研究项目中，提出了一个适用于栅长小于100 nm的体沟道、SOI沟道、薄体SOI沟道和DG MOSFET沟道中载流子迁移率的统一模型。基于包含量子效应的非平衡输运的声学物理，通过寻找表征器件中非局域输运的有效平均载流子能量，将传统的低场反型层迁移率扩展到高场区域。在包含延迟场、低场和高场的区域内，将对具有量子力学修正势的反型层中的载流子进行一系列自洽蒙特卡罗(MC)模拟。统一的沟道迁移率将以这样的方式构建，即它可以准确地预测沟道漏极端的速度过冲、反型层中的量子化效应(包括隧道效应)以及源-沟道势垒上的热电子发射限制电流密度。这一统一的沟道迁移率将被结合到用于纳米尺度体效应、SOI、薄体SOI和DG MOSFET数值模拟的量子流体力学(QHD)输运方程中。预计这项研究将提供一种一致且简单的方法，通过流体动力学(HD)公式将模拟等级从漂移-扩散转移到MC Boltzmann。该项目将实现对沟道长度为100 nm及以下的MOS器件的模拟。这种能力是下一代集成电路仿真所需要的，预计将在几年内完成。拟议中的研究还将使校园内的研究生和本科生以及通过远程学习学习P.I.S器件仿真课程的工业工程师受益。P.I.根据过去国家科学基金项目和其他行业支持的研究项目的研究成果，不断更新课程材料。

The CMOS technology is now being ushered from l8Onm node to 13Onm node. For lOOnm-l3Onm generation technology, many key issues of transistor design must be reexamined. One of them is non-equilibrium transport which takes place in nonoscale MOS devices. Because of continuous down-scaling of the device, the gate length now becomes comparable to or smaller than the inelastic mean-free-path. In this regime, the non-equilibrium /non-local transport of carriers in MOS devices requires substantially different formulation from that of the conventional one.In this research project, it is proposed to construct a unified mobility model for carriers in the channel of bulk, SOI, thin-body SOI, and DG MOSFETs applicable to gate length below lOOnm. Based on sound physics of non-equilibrium transport including quantum effects, the conventional low-field inversion layer mobility will be extended to the high-field regime by seeking an effective average carrier energy which characterizes the non-local transport occurring in the device. A series of self-consistent Monte Carlo (MC) simulations of carriers in inversion layers with a quantum mechanically corrected potential will be carried out in the region encompassing retarding-, low-, and high-fields. A unified channel mobility will be constructed in such a way that it can accurately predict velocity overshoot at the drain end of the channel, quantization effects in the inversion layer including tunneling, as well as thermionic emission-limited current density across the source-channel barrier. This unified channel mobility will then be incorporated in the quantum hydrodynamic (QHD) transport equations for numerical simulation of nanometer-scale bulk, SOI, thin-body SOI, and DG MOSFETs.It is expected that this research will provide a consistent and easy means of moving the simulation hierachy from drift-diffusion to MC Boltzmann via a hydrodynamic (HD) formulation. The project will enable simulation of MOS devices with the channel length of 100nm and below. Such capability is required of simulation of next generation of integrated circuits, which are expected in a few years.The proposed research will also benefit both graduate and undergraduate students on campus and engineers in industry who take P.I.'s device simulation course through the distance learning. The P.I. has constantly updated course materials based on research results of the past NSF projects and other research projects supported by the industry.