Simulation of High Speed Pseudomorphic Heterojunction Bipolar Transistors

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A specific objective is to extend the state-of-the-art of the numerical modeling of lattice-matched heterojunction semiconductor devices to strained-layer (pseudomorphic) heterojunction semiconductor devices for high speed and/or high frequency applications. Over the last three years, we have modeled A1GaAs/GaAs and InGaAs/InA1AsHBTs. Using a finite difference drift-diffusion equations (DDE) solver and numerical small-signal a.c. analysis, terminal characteristics as well as fT and fmax of these devices have been simulated. In view of recent interest in strained-layer semiconductors, it is natural to extend our current research to the modeling of HBTs involving strained layers. Focus will be placed on Si1-x Gex/Si and InxGa1-x As/GaAs systems. The basic heterojunction structures to be modeled are vertical devices having strained double heterojunctions with either emitter-top or collector-top configurations. The Monte Carlo method will be used to determine fundamental material properties, e.g. mobility, different coupling constants needed for proper modeling of non- stationary effects such as overshoot, and to perform full regional analysis of selected regions where these effects are suspected to be taking place, e.g. in the base-collector region of an HBT. In the next step, calculations will be performed using hydrodynamic equations obtained from the first three moments of the Boltzmann transport equation with the transport coefficients derived form the MC data. The results of these calculations will enable us to calculate both steady state d.c. and small-signal a.c. parameters, ranging from current gain to fT and fmax. Simulation results will be compared with either published data or with actual device measurements to be carried out in collaboration with researchers of the IBM Corporation. It is hoped that this research will bring heterojunctions advantages to today's well developed silicon technology and also take GaAs technology one step further in the race for the fastest semiconductor device.