Research for Mixed Signal Electronic Technologies: A Joint Initiative Between NSF and SRC: Scalable Design and Test Methods for Single-Chip Multi-Link Radio-Frequency Transceivers

混合信号电子技术研究：NSF 和 SRC 的联合倡议：单芯片多链路射频收发器的可扩展设计和测试方法

• 批准号: 0120255
• 负责人: Mani Soma
• 金额: $ 22.5万
• 依托单位: University of Washington
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2001
• 资助国家: 美国
• 起止时间: 2001-09-15 至 2005-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0120255&HistoricalAwards=false
• 关键词: Research; Mixed; Signal; Electronic; Technologies

Recent developments in mixed-signal systems, especially those integrating computing andcommunication in a system-on-a-chip, have focused on the goal to communicate information via wireless devices and networks. While digital system design to process baseband information is moving into the low gigahertz (GHz) frequency range, the mixed-signal transceivers have to operate in the ISM bands (2.5 GHz up to 5.8 GHz) with even higher frequencies in the near future to satisfy bandwidth demands. Analog design advances have produced several transceiver designs up to 5 GHz, using CMOS, BiCMOS, and other technologies. To reduce noise, these designs tend to separate the transmitter and receiver, and so far, have provided only a single physical link (one transmitter and one receiver) in a wireless device. In the design area, this proposal addresses the creation and verification of scalable systematic design methods to integrate two or more physical links on one single chip to provide more bandwidth and flexibility in communication applications. A methodology to incorporate multi-links is scalable in the sense that more links can be added by application demands. To create this methodology, we propose the following design approaches:1. Noise cancellation techniques and circuits to deal with digital switching noise.2. Noise cancellation techniques and circuits to deal with RF noise interference between different transceiver links and circuits.These circuits will be validated using case studies from industry with whom we have had closecollaborations: Texas Instruments, Motorola, and National Semiconductors, who will provideadvanced fabrication technologies and simulation models for this study.The designs will be fully tested and the development of scalable test methods is the second focus of this proposal. Mixed-signal test advances, despite intense activities, have been rather slow, especially in high-frequency (GHz) test. We propose to investigate the following approaches and distill the results into a test methodology that can be scaled with respect to operating frequencies and process advances:1. End-to-end digital test methods using one transmit link and one receive link on the same chipto verify correct information transmission.2. Designs of on-chip delay and phase measurement circuits, operating at the same frequency asthe transceivers.3. Interface between ATE and on-chip test circuits to use test resources efficiently.During the validation of these test methodologies, we will need access to advance test equipment for comparison purposes, and these equipment will be provided by our collaborator at Teradyne (Tualatin, OR) and Wavecrest (San Jose, CA).Another level of integration involves the curriculum - research aspects of the proposed work,which is being implemented in our current curriculum revision. Dissemination approaches re-used the distance learning methods and assessment supported by NSF, FIPSE, and our ownuniversity. The proposal will deliver fundamental methodologies and techniques, and train thefirst-generation system architects in high-frequency mixed-signal design and test.

混合信号系统的最新发展，特别是那些在片上系统中集成计算和通信的系统，重点关注通过无线设备和网络传递信息的目标。虽然处理基带信息的数字系统设计正在进入低千兆赫 (GHz) 频率范围，但混合信号收发器必须在 ISM 频段（2.5 GHz 至 5.8 GHz）中运行，并在不久的将来甚至更高的频率以满足带宽需求。模拟设计的进步已经产生了多种高达 5 GHz 的收发器设计，采用 CMOS、BiCMOS 和其他技术。为了降低噪声，这些设计倾向于将发射器和接收器分开，并且到目前为止，在无线设备中仅提供单个物理链路（一个发射器和一个接收器）。在设计领域，该提案致力于创建和验证可扩展的系统设计方法，以将两个或多个物理链路集成在一个芯片上，从而在通信应用中提供更多的带宽和灵活性。合并多链路的方法是可扩展的，因为可以根据应用程序需求添加更多链路。为了创建这种方法，我们提出以下设计方法：1．处理数字开关噪声的噪声消除技术和电路。2．噪声消除技术和电路，用于处理不同收发器链路和电路之间的射频噪声干扰。这些电路将使用与我们密切合作的行业案例研究进行验证：德州仪器、摩托罗拉和国家半导体，他们将为本研究提供先进的制造技术和仿真模型。设计将经过全面测试，可扩展测试方法的开发是本研究的第二个重点 提议。尽管活动频繁，但混合信号测试的进展却相当缓慢，特别是在高频 (GHz) 测试方面。我们建议研究以下方法，并将结果提炼成一种测试方法，该方法可以根据工作频率和工艺进步进行扩展：1。使用同一芯片上的一条发送链路和一条接收链路来验证信息传输正确性的端到端数字测试方法。 2．片上延迟和相位测量电路的设计，与收发器工作在相同的频率。3． ATE 和片上测试电路之间的接口，以有效地使用测试资源。在验证这些测试方法期间，我们将需要访问先进的测试设备以进行比较，这些设备将由我们在 Teradyne（俄勒冈州图拉丁）和 Wavecrest（加利福尼亚州圣何塞）的合作者提供。另一个级别的集成涉及课程 - 所提议工作的研究方面，这正在我们当前的实施中 课程修订。传播方法重新使用了 NSF、FIPSE 和我们自己的大学支持的远程学习方法和评估。 该提案将提供基本方法和技术，并培训第一代系统架构师进行高频混合信号设计和测试。