High-Frequency Low-Noise Mixed-Signal Adaptive Equalizer Towards SOC Design of Data Transmission Circuits

本研究提出以CMOS工艺设计一个1GHz的接收机均衡器，以应用于高速长传输距离收发器的系统级芯片（SOC）实现。 均衡滤波器采用模拟FIR滤波器，比目前常用的均衡滤波器速度更快。本文将讨论高速FIR滤波器设计中的挑战，包括模拟抽头延迟线和学习算法。提出了一种低噪声的错误检测方案，并将从通信理论的角度进行研究，以便更好地理解和改进。本论文亦将探讨此等化器在高速无线数位通讯上的潜在应用。此外，我们建议探索低成本的测试，诊断和表征所提出的自适应混合信号equalizer.In数据transmissions，包含数据的信号被衰减时，通过介质传输和衰减的传输距离和频率的函数的测试方法的设计。信号带宽内的频率相关衰减导致接收信号中的符号间干扰（ISI）。ISI反过来又会导致数据恢复错误，从而限制了传输距离和传输速率。为了减小ISI，必须补偿或均衡与频率相关的衰减。根据传输介质，现有技术的CMOS收发器工作在从100-Mbit/s到大约10-Gbit/s的速度范围内。目前，均衡仅用于低成本电缆（约130米的UTP 5电缆）上的低速（100至200 Mbit/s）数据传输。对于Gbit/s数量级的传输比特率，预加重滤波器已被用来提高发射机中的高频分量。多路复用技术，如多级信号和多相时钟，允许预加重滤波器工作在几百MHz，同时实现多Gbit/s的数据传输。但是，预加重滤波器增强了发射信号的高频分量，并在发射机中引入了强发射。为了避免发射问题，接收机均衡器是更理想的。接收机均衡器的主要挑战是高速均衡滤波器的设计和滤波器自适应算法的复杂性。拟议活动的更广泛影响之一是为业界提供训练有素的混合信号设计工程师。人们越来越担心混合信号电路设计领域的毕业工程师的短缺。本研究将加强大学混合信号电路设计课程，为工业界培养熟练的设计工程师。

This research proposes to design a 1GHz receiver equalizer in CMOS technology for system-on-chip (SOC) implementation of high-speed long transmission distance transceivers. Analog FIR filter will be used as the equalizing filter, which has higher speed than the equalizing filters commonly used today. This proposal will address the challenges in designing high-speed FIR filters, including analog tap delay line and the learning algorithms. A low-noise error detection scheme is proposed and will be studied in terms of communication theory for better understanding and improvements. Potential application of the proposed equalizer in high-speed wireless data communications will also be studied. In addition, we propose to explore design for test methodology for low-cost test, diagnostics, and characterization of the proposed adaptive mixed-signal equalizer.In data transmissions, the signal containing the data is attenuated when transmitted through media and the attenuation is a function of the transmission distance and frequency. Frequency dependent attenuation within the signal bandwidth causes inter-symbol-interference (ISI) in the received signal. ISI in turn causes errors in data recovery, thus limits the transmission distance and transmission rate. To reduce ISI, the frequency dependent attenuation must be compensated, or equalized.Depending on the transmission media, the state of the art CMOS transceivers operate at the speeds ranging from 100-Mbit/s to about 10-Gbit/s. Currently, equalization is only used in lower speed (100- to 200-Mbit/s) data transmission over low-cost cables (around 130-meter UTP5 cables). For transmission bit rates in the order of Gbit/s, pre-emphasizing filters have been usedto boost high frequency components in the transmitter. Multiplexing techniques, such asmultilevel signaling and multi-phase clocks, allow the pre-emphasizing filters to operate atseveral-hundred-MHz, while enabling multi-Gbit/s data transmission. But, pre-emphasizingfilter boosts the high frequency components of the transmitted signal and introduces strongemission in the transmitter. To avoid emission problems, receiver equalizer is more desirable.The main challenges of receiver equalizer are the design of high-speed equalizing filters and thecomplexity of filter adaptation algorithm.One of the broader impacts of the proposed activity is on providing trained mixed-signaldesign engineers for the industry. There has been growing concern over the expected shortage ofgraduating engineers specialized in the mixed-signal circuit design area. The proposed researchwill strengthen the mixed-signal circuit design program in university for educating skilled designengineers for industry.