Research for Mixed Signal Electronic Technologies: A Joint Initiative Between NSF and SRC: Design of High-Speed Serial-Links in CMOS

混合信号电子技术研究：NSF 和 SRC 的联合倡议：CMOS 中的高速串行链路设计

• 批准号: 0120372
• 负责人: Won Namgoong
• 金额: $ 15万
• 依托单位: University of Southern California
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2001
• 资助国家: 美国
• 起止时间: 2001-09-01 至 2004-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0120372&HistoricalAwards=false
• 关键词: Research; Mixed; Signal; Electronic; Technologies

The focus of the proposed research is on high-speed serial-links, where the goal is to maximizedata rates between IC chips. As fabrication technology improves, the challenge in next-generation serial-link design is in handling transistor mismatches and on-chip noise, both of which are expected to grow sharply. Consequently, future serial-link architectures must be able to tolerate high-levels of transistor mismatches and on-chip noise. The general approach followed by most researchers is to use advanced circuit techniques to mitigate their adverse effects. In contrast, we propose to use signal processing techniques in addition to circuit techniques to overcome these problems. This integrated design approach motivatesa new class of high-speed serial-link architecture that is fundamentally more robust to transistormismatches and on-chip noise. The proposed architecture also enjoys many other importantimplementation advantages, making it well suited for future generation high-speed serial-link systems.This research will demonstrate the feasibility and effectiveness of the proposed architecturefor reception and transmission of broadband signals. We will provide a complete design frame-work based on a clear understanding of various design options and the corresponding trade-offs in performance and implementation complexity. Furthermore, we will demonstrate the feasibility and the advantages of the proposed architecture by realizing it on silicon. Our goal is to achieve faster data rates than the fastest published serial-link system. The concepts and techniques developed in the proposed research are not limited to serial-link systems. They are easily applicable to any high-bandwidth communication systems where the symbol rates exceed the achievable on-chip clock frequency. Some specific examples of such applications are ultra-wideband and high-speed satellite communication systems.

拟议研究的重点是高速串行链路，其目标是最大限度地提高 IC 芯片之间的数据速率。随着制造技术的进步，下一代串行链路设计面临的挑战是处理晶体管失配和片上噪声，这两者预计都会急剧增长。因此，未来的串行链路架构必须能够容忍高水平的晶体管失配和片上噪声。大多数研究人员遵循的一般方法是使用先进的电路技术来减轻其不利影响。相反，我们建议除了电路技术之外还使用信号处理技术来克服这些问题。这种集成设计方法催生了新型高速串行链路架构，该架构从根本上对晶体管失配和片上噪声更加稳健。所提出的架构还具有许多其他重要的实现优势，使其非常适合下一代高速串行链路系统。本研究将证明所提出的架构用于宽带信号接收和传输的可行性和有效性。我们将在清楚了解各种设计选项以及性能和实现复杂性的相应权衡的基础上提供完整的设计框架。此外，我们将通过在硅上实现所提出的架构来展示其可行性和优势。我们的目标是实现比最快的已发布串行链路系统更快的数据速率。拟议研究中开发的概念和技术并不限于串行链路系统。它们很容易适用于符号率超过可实现的片上时钟频率的任何高带宽通信系统。此类应用的一些具体示例是超宽带和高速卫星通信系统。