Research for Mixed Signal Electronic Technologies: A Joint Initiative Between NSF and SRC: Design of High-Speed Serial-Links in CMOS

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The focus of the proposed research is on high-speed serial-links, where the goal is to maximizedata rates between IC chips. As fabrication technology improves, the challenge in next-generation serial-link design is in handling transistor mismatches and on-chip noise, both of which are expected to grow sharply. Consequently, future serial-link architectures must be able to tolerate high-levels of transistor mismatches and on-chip noise. The general approach followed by most researchers is to use advanced circuit techniques to mitigate their adverse effects. In contrast, we propose to use signal processing techniques in addition to circuit techniques to overcome these problems. This integrated design approach motivatesa new class of high-speed serial-link architecture that is fundamentally more robust to transistormismatches and on-chip noise. The proposed architecture also enjoys many other importantimplementation advantages, making it well suited for future generation high-speed serial-link systems.This research will demonstrate the feasibility and effectiveness of the proposed architecturefor reception and transmission of broadband signals. We will provide a complete design frame-work based on a clear understanding of various design options and the corresponding trade-offs in performance and implementation complexity. Furthermore, we will demonstrate the feasibility and the advantages of the proposed architecture by realizing it on silicon. Our goal is to achieve faster data rates than the fastest published serial-link system. The concepts and techniques developed in the proposed research are not limited to serial-link systems. They are easily applicable to any high-bandwidth communication systems where the symbol rates exceed the achievable on-chip clock frequency. Some specific examples of such applications are ultra-wideband and high-speed satellite communication systems.