Research for Mixed Signal Electronic Technologies: A Joint Initiative Between NSF and SRC: Design of High-Speed Serial-Links in CMOS

拟议研究的重点是高速串行链路，其目标是最大化IC芯片之间的数据速率。随着制造技术的进步，下一代串行链设计中的挑战是如何处理晶体管失配和片上噪声，这两者预计都将急剧增长。因此，未来的串行链结构必须能够容忍高水平的晶体管失配和片上噪声。大多数研究人员遵循的一般方法是使用先进的电路技术来减轻它们的不利影响。相反，除了电路技术之外，我们还建议使用信号处理技术来克服这些问题。这种集成的设计方法催生了一类新的高速串行链路架构，从根本上说，这种架构对晶体管失配和片上噪声具有更强的稳健性。该结构还具有许多其他重要的实现优势，使其非常适合于下一代高速串行链路系统。本研究将证明该结构用于宽带信号接收和发送的可行性和有效性。我们将在清楚了解各种设计选项以及相应的性能和实现复杂性权衡的基础上，提供完整的设计框架。此外，我们还将通过在硅片上实现该架构来证明该架构的可行性和优势。我们的目标是实现比发布最快的串行链系统更快的数据速率。在拟议的研究中提出的概念和技术并不局限于串行链系统。它们很容易应用于符号速率超过可实现的片上时钟频率的任何高带宽通信系统。这种应用的一些具体例子是超宽带和高速卫星通信系统。

The focus of the proposed research is on high-speed serial-links, where the goal is to maximizedata rates between IC chips. As fabrication technology improves, the challenge in next-generation serial-link design is in handling transistor mismatches and on-chip noise, both of which are expected to grow sharply. Consequently, future serial-link architectures must be able to tolerate high-levels of transistor mismatches and on-chip noise. The general approach followed by most researchers is to use advanced circuit techniques to mitigate their adverse effects. In contrast, we propose to use signal processing techniques in addition to circuit techniques to overcome these problems. This integrated design approach motivatesa new class of high-speed serial-link architecture that is fundamentally more robust to transistormismatches and on-chip noise. The proposed architecture also enjoys many other importantimplementation advantages, making it well suited for future generation high-speed serial-link systems.This research will demonstrate the feasibility and effectiveness of the proposed architecturefor reception and transmission of broadband signals. We will provide a complete design frame-work based on a clear understanding of various design options and the corresponding trade-offs in performance and implementation complexity. Furthermore, we will demonstrate the feasibility and the advantages of the proposed architecture by realizing it on silicon. Our goal is to achieve faster data rates than the fastest published serial-link system. The concepts and techniques developed in the proposed research are not limited to serial-link systems. They are easily applicable to any high-bandwidth communication systems where the symbol rates exceed the achievable on-chip clock frequency. Some specific examples of such applications are ultra-wideband and high-speed satellite communication systems.