Digital PLL with Observer-Controller Loop Filter

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The objective of this research is to develop a digital phase-locked loop (DPLL) that achieves low phase noise while being fundamentally robust to interferers and the effects of transport delays. The approach is to employ sophisticated digital control schemes so that the effects of circuit noise, external interferers, and loop latency can be explicitly modeled and accounted for in the digital feedback loop. This approach contrasts with existing loop filters, whose bandwidth is generally the only design parameter that can be modified to mitigate the effects of interferers or other undesirable non-idealities.Intellectual Merit: In the approach pursued in this project, the analog components of the DPLL are modeled as a noisy plant in state-space form. When viewed from this perspective, controlling the noisy plant to generate the desired frequency can be posed as a linear regulator problem, which is a classical problem of optimal linear control theory. The observer-controller loop filter developed in this project is broadly applicable to a wide range of existing systems that employ PLLs. Furthermore, the inherent robustness to interference of the proposed DPLL enables its use in many emerging systems such as in direct-conversion and out-phasing transmitter architectures.Broader Impacts: The research is integrated with an education program to help train both graduate and undergraduate students. The multi-disciplinary nature of the research will broaden the students' technical understanding, which will be indispensable for the next generation of engineers. The educational program also includes plans to improve the participation of undergraduate students and members of underrepresented groups.