Digital PLL with Observer-Controller Loop Filter

具有观察器控制器环路滤波器的数字 PLL

• 批准号: 1002334
• 负责人: Won Namgoong
• 金额: $ 35万
• 依托单位: University of Texas at Dallas
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-09-01 至 2014-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1002334&HistoricalAwards=false
• 关键词: Digital; PLL; Observer; Controller; Loop

The objective of this research is to develop a digital phase-locked loop (DPLL) that achieves low phase noise while being fundamentally robust to interferers and the effects of transport delays. The approach is to employ sophisticated digital control schemes so that the effects of circuit noise, external interferers, and loop latency can be explicitly modeled and accounted for in the digital feedback loop. This approach contrasts with existing loop filters, whose bandwidth is generally the only design parameter that can be modified to mitigate the effects of interferers or other undesirable non-idealities.Intellectual Merit: In the approach pursued in this project, the analog components of the DPLL are modeled as a noisy plant in state-space form. When viewed from this perspective, controlling the noisy plant to generate the desired frequency can be posed as a linear regulator problem, which is a classical problem of optimal linear control theory. The observer-controller loop filter developed in this project is broadly applicable to a wide range of existing systems that employ PLLs. Furthermore, the inherent robustness to interference of the proposed DPLL enables its use in many emerging systems such as in direct-conversion and out-phasing transmitter architectures.Broader Impacts: The research is integrated with an education program to help train both graduate and undergraduate students. The multi-disciplinary nature of the research will broaden the students' technical understanding, which will be indispensable for the next generation of engineers. The educational program also includes plans to improve the participation of undergraduate students and members of underrepresented groups.

本研究的目的是开发一种数字锁相环（DPLL），实现低相位噪声，同时从根本上是强大的干扰和传输延迟的影响。该方法是采用复杂的数字控制方案，使电路噪声的影响，外部干扰，和环路延迟可以明确建模，并在数字反馈环路占。这种方法与现有的环路滤波器，其带宽一般是唯一的设计参数，可以修改，以减轻干扰或其他不良的非idealities.Intellectual Merit的影响：在这个项目中追求的方法，模拟组件的DPLL被建模为一个嘈杂的工厂在状态空间的形式。当从这个角度来看，控制有噪声的植物，以产生所需的频率可以被视为一个线性调节器的问题，这是一个经典的最优线性控制理论的问题。在这个项目中开发的前置放大器控制器环路滤波器广泛适用于广泛的现有系统，采用PLL。此外，固有的鲁棒性干扰的建议DPLL使其在许多新兴的系统中使用，如在直接转换和异相发射机architecturs.Broader影响：这项研究是整合了教育计划，以帮助培养研究生和本科生。研究的多学科性质将拓宽学生的技术理解，这将是下一代工程师不可或缺的。教育方案还包括提高本科生和代表性不足群体成员参与的计划。