Research for Mixed Signal Electronic Technologies: A Joint Initiative Between NSF and SRC: Fast Methods of Coupled EM. Circuit and Logic Simulation for Giga-Scale

该项目旨在开发快速算法，用于快速模拟千兆级片上系统，其中耦合电路，逻辑和电磁（EM）效应（包括RLC寄生，耦合，串扰，皮肤和热效应-准静态和全波）变得越来越重要。 对于耦合电磁和电路仿真，我们提出了一种新的部分元件等效电路（PEEC）的方法。对于耦合EM和数字仿真，我们建议在EM分析中研究不同的时间步长，并使用数字事件的保守同步。更具体地说，我们的方法包括以下关键要素：开发基于积分方程的快速求解方法，使EM仿真在这些环境中变得可行，并允许在不同程度的模型复杂性下进行分层或多层EM分析。通过三角形网格细分的部分等效电路方法的变体来实现快速和分层方案。将EM仿真方案直接耦合到数字逻辑仿真，以分析电源接地层情况下的开关和接地反弹。利用EM中存在的结构和冗余，电路级以及耦合系统矩阵，以便将存储器和计算时间大幅减少到一定程度，使得严格和完整的耦合仿真对于复杂的片上系统是可行的。 灵敏度分析、降阶建模和多物理场仿真也是目标。开发优化编译技术，用于生成电路仿真的常微分方程（ODE）代码，并利用电路结构规律进行快速分层电路/EM仿真。 用于测试拟议的耦合EM/电路和EM/数字仿真的应用驱动程序将包括（1）千兆赫CMOS芯片收发器，以及（2）千兆赫数字电路的电源/接地网络，包括栅极开关活动建模。旨在开发快速而严格的EM/电路和EM/逻辑仿真，以实现下一代混合信号电路和系统的准确而高效的签核仿真，使仿真在环路设计优化和架构权衡，并最终使设计的可测试性，电磁效应变得难以表征，预测和测量。

This project aims at developing fast algorithms for rapid simulation of giga-scale systems-on-chip, where coupled circuit, logic, and electromagnetic (EM) effects (including RLC parasitics, coupling, cross talk, skin and thermal effects---both quasi-static and full-wave), are becoming increasingly important. For coupled EM and circuit simulation, we propose to investigate a novel partial-element equivalent electric circuit (PEEC) approach. For coupled EM and digital simulation, we propose to investigate variant time stepping in EM analysis and to use conservative synchronization with digital events. More specifically, our approach consists of the following key elements:Developing fast integral-equation-based solution methods that will make feasible EM simulation in these settings, and will permit hierarchical or multilevel EM analyses at varying degrees of model complexity.Implementation of fast and hierarchical schemes through a variation of the partial equivalent electric circuit method for triangular mesh tessellations.Coupling of EM simulation schemes directly to digital logic simulation in order to analyze switching and ground bounce in power-ground plane situations.Exploitation of structure and redundancies present in EM, circuit-level as well as coupled-system matrices in order to drastically reduce memory and computation time to a degree such that rigorous and complete coupled simulation will be feasible for complex-systems-on-chip. Sensitivity analysis, reduced-order modeling, and multi-physics simulations are targeted in addition.Development of optimized compilation techniques for generating ordinary differential equation (ODE) code for circuit simulation, and for exploiting the circuit structural regularity for fast hierarchical circuit/EM simulation. The application drivers for testing proposed coupled EM/circuit and EM/digital simulation will include (1) Giga-hertz CMOS transceivers on chip, and (2) Power/ground network of giga-hertz digital circuits including gate switching activity modeling.It is intended that the development of fast and rigorous EM/circuit and EM/logic simulation will enable accurate yet efficient sign-off simulation of next generation mixed-signal circuits and systems, enable simulation in the loop design optimization and architecture tradeoff, and finally enable design for testability where EM effects are becoming hard to characterize, predict, and measure.