CAREER: Synthesis-assistance and Compilation Software for Embedded Systems

职业：嵌入式系统综合辅助和编译软件

• 批准号: 0133519
• 负责人: Rajeev Barua
• 金额: --
• 依托单位: University of Maryland, College Park
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2002
• 资助国家: 美国
• 起止时间: 2002-05-01 至 2008-10-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0133519&HistoricalAwards=false
• 关键词: CAREER; Synthesis; assistance; Compilation; Software

SUMMARY: Synthesis-assistance and Compilation Software for Embedded Systems---------------------------------------------------------------------------Embedded systems promise to revolutionize our day-to-day lives with ever-increasing intelligence and connectivity at decreasing cost. Yet, many of the software technologies for embedded systems remain antiquated, from compilers that produce code whose performance and power consumption is substantially inferior to assembly language programs, to synthesis software that provides little guidance to the designer on what decisions to make. These shortcomings decrease system performance and increase time-to-market and software and hardware development cost.This project is developing fundamental technologies to propel the software for embedded systems to the next level of automation. Opportunities along two directions are being explored: increased automation of the synthesis of embedded soft cores, and new compiler strategies for the management of heterogeneous memoriesin embedded systems. When deployed, these innovations can be expected to lead to vast improvements in the time-to-market, cost and performance of embedded designs. Both directions rely on improved compileranalysis of application domains.In the first and major research direction, tools that assist the synthesis of embedded soft cores are being developed. Soft cores are general-purpose processors having parameterizable components instead of a fixed design. The project is designing software that recommends to the user the best choice of an expanded space of hardware parameters for the given soft core, in an automated manner, taking into account the target application domain. The design goal is reduced runtime and power consumption within a given silicon-area budget. For the first time ever, the software uses compiler analysis of the applications to guide its decisions, rather than an exhaustive design space explorations proposed before, resulting in a rapid and scalablemethodology.The second direction explored is the efficient compiler allocation of software-exposed heterogeneous memory. In many lower-end embedded chips, often used in micro-controllers and DSP processors, no caches are provided. Instead heterogeneous memory units such as scratch-pad SRAM, internal DRAM, external DRAM andROM are memory-mapped to different parts of the address space. Prior to this work, it was left to the user to partition the data among the different memory units. This project is developing a compiler strategy that automatically partitions the data among the memory units. This CAREER research also includes a strong educational component that serves college students, industry and local high schools. To this end, several initiatives are pursued. First, a new graduate course on compilers for embedded systems has been designed. It continues to evolve with the integration of new research results. Second, undergraduates are recruited for summer internships to participate in the research. Third, a new laboratory course focuses on the design of embedded soft cores and uses software developed in the research, when complete, as an educational tool. Fourth, a research seminar series is conducted for high school juniors and seniors, using short examples of futuristic applications to excite studentsabout research in computer engineering.

总结：嵌入式系统的合成辅助和编译软件- 然而，许多用于嵌入式系统的软件技术仍然过时，从编译器产生的代码的性能和功耗大大低于汇编语言程序，合成软件，提供什么样的决策，设计师很少指导。 这些缺点降低了系统性能，增加了产品上市时间和软硬件开发成本。本项目正在开发基础技术，以推动嵌入式系统软件的自动化水平。 机会沿着两个方向正在探索：增加自动化的嵌入式软核的合成，和新的编译器策略的异构memoriesin嵌入式系统的管理。 部署后，这些创新预计将大大改善嵌入式设计的上市时间、成本和性能。 这两个方向都依赖于改进的应用领域的编译器分析。在第一个和主要的研究方向，正在开发的工具，协助嵌入式软核的合成。软核是具有可参数化组件而不是固定设计的通用处理器。 该项目正在设计软件，以自动化的方式，考虑到目标应用领域，为用户推荐给定软核的硬件参数扩展空间的最佳选择。 设计目标是在给定的硅面积预算内减少运行时间和功耗。该软件首次使用编译器对应用程序的分析来指导其决策，而不是以前提出的详尽的设计空间探索，从而产生了快速和可扩展的方法。在许多低端嵌入式芯片中，通常用于微控制器和DSP处理器，没有提供缓存。 相反，异构内存单元，如暂存SRAM，内部DRAM，外部DRAM和ROM的内存映射到地址空间的不同部分。 在这项工作之前，它留给用户在不同的内存单元之间划分数据。 这个项目正在开发一种编译器策略，它可以自动将数据划分到内存单元中。 这项职业研究还包括一个强大的教育组成部分，为大学生，工业和当地高中。为此，采取了若干举措。 首先，设计了一门新的嵌入式系统编译器研究生课程。 它随着新的研究成果的整合而不断发展。 第二，招募本科生参加暑期实习。 第三，一个新的实验室课程侧重于嵌入式软核的设计，并使用在研究中开发的软件，完成后，作为一个教育工具。 第四，为高中三年级和四年级学生举办了一系列研究研讨会，使用未来应用程序的简短例子来激发学生对计算机工程研究的兴趣。