CSR-PSCE,SM: Compiler-Directed System Optimization of a Highly-Parallel Fine-Grained Chip Multiprocessor

CSR-PSCE,SM：高度并行细粒度芯片多处理器的编译器导向系统优化

• 批准号: 0834373
• 负责人: Rajeev Barua
• 金额: $ 40万
• 依托单位: University of Maryland, College Park
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-09-01 至 2012-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0834373&HistoricalAwards=false
• 关键词: CSR; PSCE; SM; Compiler; Directed

Accelerating single programs on multicore processors remains an outstanding challenge in computer systems design. Unfortunately, existing parallel systems achieve little speedup on programs other than regular dense-matrix codes. And, most of the world's programs are in this category, broadly termed non-regular code. Of course some non-regular codes have little parallelism beyond instruction level parallelism (ILP); hence no speedup is possible on multicores. However in other non-regular code, parallelism is present but is not exploitable. Reasons include high synchronization costs, non-loop parallelism, non-array data structures, recursively expressed parallelism and parallelism that is too fine-grained to be exploitable. Previous work by the PIs presented the PRAM-based XMT parallel architecture which has demonstrated good speedups on non-regular codes: 23X on breadth-first search in graphs and 9X for finding spanning tree in graphs, using 64 processors vs. the best-in-class serial processor.This project is developing new compiler technologies for XMT to achieve scalable performance in the face of architecture decisions made for scalability. It is studying better compiler techniques to achieve scalable performance for UMA architectures such as XMT. These include better task schedulers using global queues rather than work stealing; improved pre-fetching tailored for XMT's unique memory hierarchy; and using scalable non-cache-coherent Scratch-Pad Memory local to each XMT processor to reduce the need to go to expensive remote memory.The broader impacts of this project are (i) the development of compiler technologies necessary to reduce the research risk of XMT to the point where industry is willing to commercialize the technology; (ii) the delivery of scalable speedups for erstwhile hard-to-parallelize applications; (iii) the demonstration of technologies for robust performance across large classes of serial, regular parallel, and non-regular parallel programs; (iv) demonstrating a serious contender for a future universal desktop architecture; and (v) educational and outreach initiatives to popularize XMT and improve the skills of the future workforce.

在多核处理器上加速单个程序仍然是计算机系统设计中的一个突出挑战。 不幸的是，现有的并行系统实现的程序比其他定期密集矩阵代码的加速。而且，世界上大多数程序都属于这一类，广义上称为非常规代码。当然，一些非常规代码除了指令级并行（ILP）之外几乎没有并行性;因此在多核上不可能加速。然而，在其他非常规代码中，并行性是存在的，但不可利用。原因包括高同步成本、非循环并行性、非数组数据结构、递归表示的并行性和粒度太细而无法利用的并行性。PI先前的工作提出了基于PRAM的XMT并行架构，该架构在非常规代码上表现出良好的加速比：使用64个处理器与同类最佳串行处理器相比，在图中的广度优先搜索方面有23倍的加速比，在图中查找生成树方面有9倍的加速比。它正在研究更好的编译器技术，以实现XMT等UMA架构的可扩展性能。 其中包括使用全局队列而不是工作窃取的更好的任务调度器;为XMT独特的内存层次结构量身定制的改进的预取;并使用可扩展的非缓存一致性缓冲垫内存本地到每个XMT处理器，以减少需要去昂贵的远程内存。开发必要的编译器技术，以降低XMT的研究风险，使工业界愿意将该技术商业化;（ii）为以前难以并行化的应用程序提供可扩展的加速;（iii）演示跨大类串行、常规并行和非常规并行程序的强大性能的技术;（iv）演示未来通用桌面架构的有力竞争者;及（v）推广XMT及提高未来劳动力技能的教育及外展计划。