High-Level Optimization for DSP Architectures

嵌入式系统要求处理器具有最高的性能，但对功耗和芯片成本的限制很小。使用软件流水线技术，高性能的数字信号处理器通常可以利用相当大的指令级并行性(ILP)，从而显著提高性能。然而，软件流水线有时不能有效地利用处理器，可能会阻碍低功耗和低芯片成本的目标，软件流水线的问题可以通过使用先进的编译器循环转换技术来改善。然而，目前还缺乏应用循环变换的方法。应用循环变换的指标不能有效地对高性能数字信号处理(DSP)架构和软件流水线的效果进行建模。本研究将通过开发和实验验证以下几个方面来解决上述问题：1)一种在高性能DSP体系结构上准确模拟软件流水线循环性能的性能度量。2)在应用高级循环变换之前对软件流水线循环的寄存器压力的预测。作为这项研究的结果，将在DSP应用程序中利用更多的ILP，从而提高性能并节省执行应用程序所需的总能量。在性能和能源使用方面的改进将允许在嵌入式系统中使用更好和更昂贵的算法。

Embedded systems require maximum performance from a processor withinsignificant constraints in power consumption and chip cost. Usingsoftware pipelining, high-performance digital signal processors canoften exploit considerable instruction-level parallelism (ILP), andthus significantly improve performance. However, software pipeliningsometimes fails to utilize the processor efficiently and may hinderthe goals of low power consumption and chip cost.The problems with software pipelining can be ameliorated by usingadvanced compiler loop transformation techniques. However, currentmethods for applying loop transformations are lacking. Metrics forapplying loop transformations do not model high-performance digitalsignal processing (DSP) architectures and the effects of softwarepipelining effectively. This research will address the above problems by developingand experimentally validating the following:1) A performance metric that accurately models software-pipelinedloop performance on high-performance DSP architectures. 2) A prediction of the register pressure of a software-pipelinedloop before high-level loop transformations are applied.As a result of this research, more ILP will be exploited in DSPapplications, resulting in an increase in performance and a savings inthe overall energy required to execute an application. Improvements inperformance and energy usage will allow better and morecomputationally expensive algorithms to be used in embedded systems.