High-Level Optimization for DSP Architectures

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Embedded systems require maximum performance from a processor withinsignificant constraints in power consumption and chip cost. Usingsoftware pipelining, high-performance digital signal processors canoften exploit considerable instruction-level parallelism (ILP), andthus significantly improve performance. However, software pipeliningsometimes fails to utilize the processor efficiently and may hinderthe goals of low power consumption and chip cost.The problems with software pipelining can be ameliorated by usingadvanced compiler loop transformation techniques. However, currentmethods for applying loop transformations are lacking. Metrics forapplying loop transformations do not model high-performance digitalsignal processing (DSP) architectures and the effects of softwarepipelining effectively. This research will address the above problems by developingand experimentally validating the following:1) A performance metric that accurately models software-pipelinedloop performance on high-performance DSP architectures. 2) A prediction of the register pressure of a software-pipelinedloop before high-level loop transformations are applied.As a result of this research, more ILP will be exploited in DSPapplications, resulting in an increase in performance and a savings inthe overall energy required to execute an application. Improvements inperformance and energy usage will allow better and morecomputationally expensive algorithms to be used in embedded systems.