Network Processors: Architecture and Design

有两种力量加剧了与包处理相关的问题。首先，对更高带宽和线路速率的需求挑战了我们执行实时数据包处理的能力。其次，正在定义更复杂的功能需求和服务，这大大增加了分组计算需求。作为回应，现代路由器正在配备网络处理器（NPs），它既包括通用多处理功能，也包括特殊硬件功能。np挑战了我们设计能力的极限。本研究旨在量化NP设计，并开发一种性能驱动的方法，该方法既认识到物理限制（例如，面积，功率），也认识到分组应用的计算要求。研究了主要的体系结构方法（并行、流水线、指令专门化），并开发了利用这些体系结构范例的设计过程。NP体系结构模型以及相关的基准测试导致了连贯的NP设计方法，并扩展了我们对实时计算机设计的理解。该研究直接有利于快速发展的NP和路由器设计领域，提高网络性能。所使用的技术是经典计算机体系结构的技术，包括设计约束的形式化、设计模型的开发以及定量模型参数化的基准的使用。

Two forces have exacerbated problems associated with packet processing. First, demands for higher bandwidth and line rates challenge our abilities to perform real-time packet processing. Second, more complex functional requirements and services are being defined that significantly increase packet computational demand. In response, modern routers are being equipped with Network Processors (NPs) that include both general-purpose multiprocessing and special hardware capabilities. NPs push the envelope of our design capabilities. This research aims at quantifying NP design and at developing a performance driven methodology that is cognizant of both physical constraints (e.g., area, power) and the computational requirements of packet applications.Principal architectural approaches (parallelism, pipelining, instruction specialization) are investigated and design procedures for exploiting these architectural paradigms are developed. The NP architecture models along with associated benchmarking lead to a coherent NP design methodology and extend our understanding of real-time computer design.The research directly benefits the rapidly expanding area of NP and router design, and network performance. The techniques utilized are those of classical computer architecture, including the formalization of the design constraints, development of design models, and the use of benchmarks for quantitative model parameterization.